NVMe Storage Controller Clock Gating for Lower Power Queues
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Solution Overview
Problem
Existing semiconductor memory devices face high power consumption due to unnecessary activation of clocks in various intellectual property blocks, which are not optimized based on their operation states.
Innovation Solution
A storage controller that selectively activates or deactivates multiple clocks depending on the operation states of different function blocks within the NVMe control unit, such as the command fetch, DMA engine, and interrupt blocks, thereby reducing power consumption by ensuring clocks are only provided when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clocks are continuously provided to all intellectual property blocks, then operational readiness and response time are improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic clock gating that selectively activates or deactivates clocks to different intellectual property blocks based on their current operational state. The clock managing unit monitors operation phases and adjusts clock distribution in real-time, ensuring clocks are provided only when blocks need to operate, thus reducing power consumption while maintaining operational readiness.
Solution Approach 2:
The system employs periodic clock activation where clocks are provided to intellectual property blocks only during specific operation phases when needed. The clock managing unit activates clocks for particular blocks based on the current operation phase (e.g., fetching commands, executing operations, writing completion information), creating a periodic rather than continuous clock distribution pattern that reduces overall power consumption.
2Use of energy by moving object
If clocks are selectively activated based on operation states, then power consumption is reduced, but system complexity increases
Solution Approach 1:
The patent segments the clock distribution control into a dedicated clock managing unit that independently handles clock activation for different intellectual property blocks. This segmentation allows the complex control logic to be isolated in a specialized unit rather than distributed throughout the entire system, making the complexity manageable and localized while achieving power reduction through selective clock activation.
Data Source
AI summary
A storage controller communicates with an external device including a submission queue and a completion queue. An operation method of the storage controller includes receiving a notification associated with a command from the external device, based on a first clock, fetching the command from the submission queue, based on a second clock, performing an operation corresponding to the fetched command, based on a third clock, writing completion information to the completion queue, based on a fourth clock, and transmitting an interrupt signal to the external device, based on a fifth clock. Each of the first clock to the fifth clock is selectively activated depending on each operation phase.