Non-volatile Memory Validity Timing

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Solution Overview

Problem

Newer types of non-volatile random access memory (NVRAM) such as STT-RAM and MRAM face a tradeoff where higher power usage ensures long-term information retention, while minimal power usage results in short-term retention, posing challenges for battery-powered devices that need to maintain memory reliability with minimal power consumption.

Innovation Solution

A method is developed to determine the persistence time of non-volatile memory contents and use this timing information to determine refresh timing and predict the remaining useful life of the memory, allowing for optimized power management and reliability assessment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If higher power is used to write data to NVRAM, then long-term information retention is achieved, but power consumption increases

Engineering Contradiction:
Improveinformation retentionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system performs preliminary validation by reading back data immediately after writing and checking it against expected values. Timing information is recorded in advance to establish validity windows, allowing the system to proactively identify and correct potential retention failures before they occur, thereby achieving reliable long-term retention without continuously applying power.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms by reading data from NVRAM and validating it against timing information and expected values. This feedback loop allows the system to monitor retention quality over time and adjust power management strategies accordingly, maintaining reliability while minimizing unnecessary power consumption during validation periods.

Inventive Principle:
Principle #23Feedback

2Use of energy by moving object

If minimal power is used to write data to NVRAM, then power consumption is reduced, but information retention becomes short-term

Engineering Contradiction:
Improvepower consumptionVSAvoidinformation retention
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The system performs preliminary validation by reading back data immediately after writing and checking it against expected values. Timing information is recorded in advance to establish validity windows, allowing the system to proactively identify and correct potential retention failures before they occur, thereby achieving reliable long-term retention without continuously applying power.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms by reading data from NVRAM and validating it against timing information and expected values. This feedback loop allows the system to monitor retention quality over time and adjust power management strategies accordingly, maintaining reliability while minimizing unnecessary power consumption during validation periods.

Inventive Principle:
Principle #23Feedback

3Reliability

If continuous power is applied to NVRAM, then information retention is maintained, but battery life is reduced

Engineering Contradiction:
Improvememory reliabilityVSAvoidbattery life
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

Instead of continuous power application, the system uses periodic validation operations where data is read and checked at specific intervals based on recorded timing information. This periodic approach maintains memory reliability by detecting retention failures when they occur while allowing the system to enter low-power states between validations, thereby extending battery life.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The NVRAM system performs self-validation by reading its own data and checking it against stored timing information and expected values. This self-service mechanism allows the memory to autonomously monitor its own retention quality without requiring continuous external power or control, enabling the system to power down during validation periods and extend overall battery life.

Inventive Principle:
Principle #25Self-service

4Reliability

If periodic validation is performed on NVRAM, then retention quality is monitored, but system operation time is reduced

Engineering Contradiction:
Improveretention qualityVSAvoidsystem operation time
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

Instead of continuous power application, the system uses periodic validation operations where data is read and checked at specific intervals based on recorded timing information. This periodic approach maintains memory reliability by detecting retention failures when they occur while allowing the system to enter low-power states between validations, thereby extending battery life.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system performs preliminary validation by reading back data immediately after writing and checking it against expected values. Timing information is recorded in advance to establish validity windows, allowing the system to proactively identify and correct potential retention failures before they occur, thereby achieving reliable long-term retention without continuously applying power.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9373375B2Non-volatile memory validity
Publication Date: 2016.06.21 LENOVO SWITZERLAND INTERNATIONAL GMBH
  • US9373375B2 patent drawing
  • US9373375B2 patent drawing
  • US9373375B2 patent drawing

AI summary

An embodiment provides a method, including: reading validity timing information written to a non-volatile memory device; and determining validity of the non-volatile memory device using the validity timing information read from the non-volatile memory device. Other aspects are described and claimed.