N-well implants isolate flash memory blocks to reduce erase current
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Solution Overview
Problem
Flash memory devices face issues with high current requirements during erase operations and disturb conditions due to shared substrate capacitance and unselected memory block coupling, limiting the number of erase cycles and causing potential data loss.
Innovation Solution
Implanting n-wells in source lines to isolate memory blocks and create sub-regions, reducing capacitance and isolating voltage application to individual blocks, thereby minimizing current consumption and disturb conditions during erase and program operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If all memory blocks share the same substrate, then device integration is achieved, but large capacitance requires high current and time for erase operations
Solution Approach 1:
The patent divides the shared substrate into multiple isolated sub-regions using n-well implants and isolating strips. Each sub-region contains specific source lines and memory blocks, separating the previously unified substrate into independent segments that can be operated independently, thereby reducing the capacitance that must be charged during erase operations.
Solution Approach 2:
The patent extracts the capacitance problem by isolating specific source lines and memory blocks into separate sub-regions with their own n-well implants. This extraction removes the unnecessary capacitance from the erase operation, allowing only the required sub-region to be charged rather than the entire substrate, thus reducing current consumption.
2Device complexity
If all memory blocks share the same substrate, then device integration is achieved, but erase disturb conditions limit the number of erase cycles
Solution Approach 1:
The patent segments the substrate into isolated sub-regions using n-well implants and isolating strips, preventing voltage coupling between adjacent memory blocks. This segmentation ensures that during erase operations on one block, other blocks are electrically isolated and do not experience disturb conditions, thereby improving reliability and extending the number of usable erase cycles.
Solution Approach 2:
The n-well implants and isolating strips act as intermediary structures between adjacent memory blocks. These intermediaries provide electrical isolation, preventing the propagation of high voltage signals from selected blocks to unselected blocks, thus eliminating erase disturb conditions and improving erase cycle durability.
3Ease of operation
If unselected word lines are left floating during erase, then operation simplicity is maintained, but coupling from substrate charges word lines to high state creating disturb conditions
Solution Approach 1:
The patent extracts the harmful coupling effect by introducing n-well implants and isolating strips that remove the electrical connection between the substrate and unselected memory blocks. This extraction prevents the substrate voltage from coupling to floating word lines in unselected blocks, eliminating the disturb condition while maintaining operational simplicity.
Solution Approach 2:
The n-well implants and isolating strips serve as intermediary barriers between the substrate and unselected memory blocks. These intermediaries block the harmful voltage coupling that would otherwise charge floating word lines to high states, preventing erase disturb conditions without complicating the erase operation procedure.
Data Source
AI summary
A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells.