On-Chip Clock Controller for Memory Interface Testing
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Solution Overview
Problem
The complexity of circuit testing in memory devices, particularly in scan mode, makes it challenging to detect faults in memory interface paths due to advanced clocking methods, which complicate static timing analysis and physical design, and require excessive time and effort.
Innovation Solution
An integrated circuit with an on-chip clock controller (OCC) that provides mutually exclusive clock signals during scan capture mode, allowing for efficient testing of memory interfaces without balancing functional and test clocks, and enabling detection of faults without masking violating paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If advanced clocking methods are used in memory devices, then functional performance is improved, but testing complexity increases
Solution Approach 1:
The patent segments the clocking system into two distinct clock domains: a functional clock for normal operation and a test clock for testing operations. This segmentation allows independent optimization of each domain, enabling advanced functional clocking while simplifying testing by using a separate, dedicated test clock that does not inherit the complexity of the functional clocking scheme.
2Adaptability or versatility
If both functional pins and test pins are active during scan capture mode, then testing capability is improved, but timing analysis difficulty increases
Solution Approach 1:
The patent introduces a test clock domain as an intermediary between the functional clock domain and the testing operations. During scan capture mode, the test clock serves as a mediator that drives both functional pins and test pins independently, allowing them to be simultaneously active without creating direct timing conflicts. This intermediary clock domain simplifies timing analysis by providing a clear, dedicated clock reference for all testing operations.
3Measurement precision
If clock balancing and masking are required for testing, then fault detection accuracy is improved, but design effort increases
Solution Approach 1:
The patent extracts the testing operations from the functional clock domain and places them in a separate test clock domain. This extraction eliminates the need for clock balancing between functional and test clocks, as they operate independently. The test clock domain can be optimized specifically for testing requirements without being constrained by functional performance requirements, thereby reducing design effort while maintaining fault detection accuracy.
Data Source
AI summary
In some embodiments, an integrated circuit may include a memory self-testing circuit and a memory having a plurality of data storage locations, each location having a unique address. The integrated circuit may further include an output including at least one register capable of storing an address of a memory location where an error has been detected during execution of the memory self-testing circuit. Further, the integrated circuit may include an on-chip clock controller (OCC) circuit including a first output to provide a first clock signal and a second output to provide a second clock signal according to a mode of operation. In a scan mode, the OCC circuit may be configured to enable the first clock signal and the second clock signal and to selectively enable the first clock signal and the second clock signal to be mutually exclusive during a scan capture portion of the scan mode.