Odd-Division Frequency Divider Circuit With 50% Duty Cycle
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Solution Overview
Problem
Existing frequency divider circuits based on Johnson ring architecture face challenges in generating clock signals with a 50% duty cycle for odd number divisions, such as divide-by-5, which is essential for many digital processing applications.
Innovation Solution
A circuit comprising a chain of N+1 D-type latches arranged in pairs, with a memory element and an AND gate configuration that allows for programmable division by odd or even numbers, ensuring the output clock signal has a 50% duty cycle by adjusting the set and reset inputs based on rising and falling edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a Johnson ring architecture is used for frequency division, then the circuit can achieve simple structure for even number divisions, but it cannot generate 50% duty cycle output for odd number divisions
Solution Approach 1:
The circuit is segmented into two functional parts: a Johnson ring counter for frequency division and a duty cycle correction circuit. The correction circuit is further segmented into edge detection circuits (for rising and falling edges) and a control circuit that generates correction signals. This segmentation allows the Johnson ring to handle even number divisions simply while the correction circuit independently handles the duty cycle adjustment for odd number divisions.
Solution Approach 2:
Edge detection circuits serve as intermediaries between the Johnson ring counter output and the final output. These intermediaries detect the rising and falling edges of the counter output and generate corresponding correction signals that are fed back to the Johnson ring counter. This intermediary mechanism enables the system to achieve 50% duty cycle without fundamentally changing the Johnson ring architecture.
2Adaptability or versatility
If an AND gate is added to achieve odd number division (e.g., divide-by-5), then the division function is achieved, but the duty cycle becomes 40% which is unsuitable for many applications
Solution Approach 1:
The circuit employs feedback mechanisms where edge detection circuits monitor the output of the Johnson ring counter and feed correction signals back to the counter inputs. When the counter produces an odd number division with non-50% duty cycle, the feedback mechanism detects the edge transitions and generates correction pulses that adjust the counter state, thereby correcting the duty cycle to 50% while maintaining the odd number division ratio.
Solution Approach 2:
The circuit changes the timing parameters of the counter transitions through feedback control. By detecting edge transitions and generating correction signals at specific moments, the circuit effectively changes the duration of high and low states in the output waveform, transforming the duty cycle from 40% to 50% without altering the fundamental division ratio.
3Reliability
If latches are arranged in pairs with edge-triggered configuration, then the circuit can achieve precise clocking synchronization, but the circuit complexity increases
Solution Approach 1:
Each latch pair is designed to perform multiple functions: frequency division, edge detection, and duty cycle correction. The first latch in each pair detects rising edges while the second latch detects falling edges, and both functions are integrated into the same structural unit. This multi-functionality reduces the need for separate components and simplifies the overall circuit architecture despite the enhanced functionality.
Data Source
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AI summary
A circuit for deriving an output clock signal from an input clock signal, the output clock 5 signal having a frequency which is 1/Nth of the frequency of the input clock signal, where N is an odd number. The circuit comprises a plurality o f latches configured as a latch ring, the latches being arranged in successive pairs, each pair of latches comprising a first latch that switches on one of the rising or falling edge of the input clock signal, and a second latch that switches on the other of the rising or falling edge of 10 the input clock signal. An RS flip flop is coupled to receive at one of its set and reset inputs an output from the latch ring that is switched on a rising edge, and at the other of the set and reset inputs an output from the latch ring that is switched on a falling edge. Said output clock signal is provided at an output of the RS flip flop.