ODT Clock Gating for Low-Power Memory Termination Control
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Solution Overview
Problem
As semiconductor memory devices operate at higher speeds, signal impedance mismatching due to external noise, source voltage variations, and manufacturing process variations leads to signal reflection and distortion, causing issues like setup/hold failures and judgment errors, and existing technologies struggle to efficiently manage current consumption during inactivation of ODT blocks or DLLs.
Innovation Solution
An on-die termination (ODT) control device that includes a mode register set, clock control unit, and ODT control unit to generate and control clock signals, reducing unnecessary current consumption by selectively supplying clock signals to the ODT block or DLL based on their activation status.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock signals are continuously supplied to the ODT control unit, then the ODT block can respond quickly when activated, but unnecessary current consumption occurs when the ODT block or DLL is inactivated
Solution Approach 1:
The patent implements periodic action by selectively supplying clock signals to the ODT control unit based on the activation status of the ODT block or DLL. When either block is activated, clock signals are supplied to maintain operational readiness; when both are inactivated, clock supply is stopped to eliminate unnecessary current consumption. This periodic clocking strategy resolves the contradiction between maintaining fast response capability and reducing power consumption during idle periods.
2Reliability
If impedance matching is implemented using external fixed resistors, then signal reflection is reduced, but aging, temperature variation, and manufacturing process variation cause impedance mismatching
Solution Approach 1:
The patent applies parameter changes by replacing fixed external resistors with variable on-chip termination resistors whose resistance values can be dynamically adjusted. The ODT block controls the impedance of termination resistors by turning on or off specific transistors in parallel configurations, allowing the impedance to be adapted to compensate for variations due to aging, temperature, and manufacturing processes. This dynamic parameter adjustment resolves the contradiction between achieving good impedance matching and maintaining stability under varying conditions.
3Speed
If the swing range of interface signals is narrowed to minimize delay time, then signal transfer speed is improved, but the influence of external noise and signal reflection increases
Solution Approach 1:
The patent applies local quality by implementing termination resistance control at the specific location of the interface terminal where signal reflection occurs. The ODT block provides localized impedance matching at the termination point, which effectively suppresses signal reflection and noise influence without requiring a wider signal swing range. This localized intervention resolves the contradiction between maintaining narrow swing ranges for high speed and reducing the impact of external noise and reflection.
Data Source
AI summary
An on die termination (ODT) control device includes a mode register set for generating a clock control signal based on mode set information; a clock control unit for receiving an internal clock signal and a delay locked loop (DLL) clock signal and outputting an intermediate internal clock signal and an intermediate DLL clock signal in response to the clock control signal; and an ODT control unit for controlling an ODT block by receiving an ODT control signal in response to the intermediate internal clock signal and the intermediate DLL clock signal.