Off-Die Clock Test Circuit With PLL Frequency Synthesis
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Solution Overview
Problem
Existing wafer probe technologies are limited in delivering clock signals at frequencies matching those required for semiconductor dies with off-die clocks, potentially leading to inadequate testing and stacking of defective dies.
Innovation Solution
Incorporating a Phase-Locked Loop (PLL) or similar device multiplexed with the forwarded clock signal at the base of the clock distribution network, which is active only during testing and inactive during operational mode, allowing for accurate die testing without power wastage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a wafer probe is used to provide clock signal to the die during testing, then the die can be tested before stacking, but the probe cannot deliver clock signal at the required frequency
Solution Approach 1:
A clock synthesizer is introduced as an intermediary component on the die to convert the low-frequency clock signal from the wafer probe into the high-frequency clock signal required for accurate die testing. This mediator enables the wafer probe to function effectively despite its frequency limitations.
Solution Approach 2:
The clock synthesizer changes the frequency parameter of the clock signal, transforming it from the probe's limited frequency range to the required operating frequency range for accurate die testing.
2Reliability
If a clock synthesizer is integrated on the die for testing, then accurate clock frequency can be achieved, but power is consumed during operational mode when not needed
Solution Approach 1:
The clock synthesizer's operational state is made dynamic - it is enabled only during testing mode and disabled during operational mode. This dynamic control eliminates unnecessary power consumption while maintaining testing accuracy when needed.
Solution Approach 2:
The clock synthesizer operates periodically - activated during testing phases and deactivated during normal operational phases - thereby consuming power only when necessary for accurate testing.
3Reliability
If clock synthesizer is always active on the die, then testing can be performed accurately, but device complexity and power wastage increase
Solution Approach 1:
The clock synthesizer is integrated with mode control logic that dynamically enables it only during testing operations. This dynamic activation reduces the effectively active circuit complexity and eliminates continuous power consumption while maintaining testing accuracy.
4Ease of manufacture
If wafer probe is used for testing, then manufacturing process is simple, but defective dies may be stacked due to inadequate testing
Solution Approach 1:
The clock synthesizer serves as an intermediary that enhances the wafer probe's testing capability by providing the required clock frequency, thereby ensuring accurate defect detection while maintaining the simplicity of the wafer probe testing approach.
Solution Approach 2:
By changing the clock signal frequency parameter through the synthesizer, the testing capability is enhanced to detect defects that would be missed by direct probe testing, thereby improving die quality assurance without complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate testing of semiconductor dies with off-die clocks by matching the clock frequency, ensuring only known-good dies are stacked, thereby improving manufacturing efficiency and reducing waste.
Implementation Method 1
Incorporating a Phase-Locked Loop (PLL) or similar device multiplexed with the forwarded clock signal at the base of the clock distribution network, which is active only during testing
Data Source
AI summary
A device can include a clock synthesizer and a clock signal multiplexer that is configured to provide a signal from the clock synthesizer as output during a test mode and to provide a forwarded clock signal as output during an operational mode. Various other devices, systems, and methods are also disclosed.