Offset Bond Pad Isolation Structure for BSI-CIS Light Leakage Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The fabrication of back-side illuminated CMOS image sensors (BSI-CIS) is complicated and costly due to the need for dielectric structures around bond pads, which can increase light reflection and decrease the reliability of the bond, while placing bond pads on the substrate surface can affect photodetector efficiency and reliability.

Innovation Solution

A bond pad isolation structure is laterally offset from photodetectors, surrounded by a ring-shaped dielectric structure that extends from the front-side to the back-side of the substrate, electrically isolating the bond pad from other devices and reducing current leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dielectric structures are placed around bond pads, then electrical isolation is improved, but light reflection increases and manufacturing complexity increases

Engineering Contradiction:
Improveelectrical isolationVSAvoidlight reflection
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the dielectric structure from the bond pad region by laterally offsetting it, removing the harmful interaction between dielectric materials and incident light while preserving the electrical isolation function through alternative positioning

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from vertical stacking (dielectric over bond pad) to lateral separation (dielectric offset from bond pad), using spatial repositioning to eliminate light reflection while maintaining electrical isolation through the offset configuration

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If dielectric structures are placed around bond pads, then electrical isolation is improved, but device complexity increases

Engineering Contradiction:
Improveelectrical isolationVSAvoidfabrication complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the bond pad isolation function with the photodetector isolation structure, using a shared offset dielectric configuration to achieve both electrical isolation objectives simultaneously and reduce overall device complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The offset dielectric structure serves multiple functions: it provides electrical isolation for the bond pad, maintains isolation for photodetectors, and reduces light reflection, thereby simplifying the overall device architecture through multi-functionality

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If bond pads are placed on substrate surface, then electrical connection is improved, but photodetector efficiency decreases

Engineering Contradiction:
Improvebond reliabilityVSAvoidphotodetector efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the substrate into distinct functional regions with lateral offset: bond pad regions for electrical connection and photodetector regions for light sensing, allowing each to optimize its performance without interfering with the other

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250357399A1Isolation structure for bond pad structure
Publication Date: 2025.11.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250357399A1 patent drawing
  • US20250357399A1 patent drawing
  • US20250357399A1 patent drawing

AI summary

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor device including a shallow trench isolation (STI) structure disposed between a first side and a second side of the semiconductor substrate. An intermetal dielectric structure comprising a first metal interconnect is on the second side. A first etching process is performed to form a first trench extending from the first side of the semiconductor substrate to the STI structure. An etch stop layer is deposited on the first side. A dielectric material is deposited into the first trench to form a dielectric spacer. A second trench is etched during a second etching process. The second trench is aligned with the first trench and extends through the STI structure to the first metal interconnect. A conductive material is deposited into the second trench to form a contact pad that contacts the first metal interconnect.