Offset-Stacked Semiconductor Packages With Crack-Blocking Adhesive
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Solution Overview
Problem
Existing semiconductor packages face challenges in maintaining structural integrity and reliability due to the generation of cracks during the stacking of multiple semiconductor chips, particularly when the chips are aligned in an offset stack structure, which can lead to reduced performance and durability.
Innovation Solution
The implementation of an adhesive member with an extension that contacts and overlaps with the side surfaces of underlying semiconductor chips, preventing direct contact between the chips and an encapsulant, thereby reducing the likelihood of crack formation and enhancing the structural integrity of the package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips are stacked in an offset stack structure to achieve miniaturization, then the device density and integration are improved, but cracks are generated at the interfaces between chips, compromising structural integrity and reliability
Solution Approach 1:
An adhesive member is introduced as an intermediary substance between the semiconductor chips in the offset stack structure. This adhesive member fills the gaps and interfaces between chips, preventing crack generation while maintaining the compact offset stacking arrangement, thus preserving both device density and structural integrity
Solution Approach 2:
The adhesive member is applied in advance to the lower surface of upper semiconductor chips before stacking. This pre-application creates a protective cushioning layer that prevents cracks from forming at interfaces during the stacking process and under subsequent mechanical stress, maintaining reliability in the miniaturized structure
2Reliability
If adhesive members are applied to lower surfaces of semiconductor chips to prevent cracks, then structural integrity and reliability are improved, but the complexity of the manufacturing process increases
Solution Approach 1:
The adhesive member is applied to the lower surface of each semiconductor chip as a preliminary action before the stacking process. This pre-coating approach simplifies the overall manufacturing process by ensuring proper adhesion and crack prevention is built into the structure from the beginning, rather than requiring additional post-processing steps
Solution Approach 2:
The adhesive member's physical parameters (such as viscosity, curing temperature, or composition) can be optimized to achieve the desired balance between reliability improvement and manufacturing simplicity. By adjusting these parameters, the adhesive can be applied using standard manufacturing techniques without significantly increasing process complexity
Data Source
AI summary
A semiconductor package includes a package substrate, a first semiconductor chip and a second semiconductor chip sequentially stacked on the package substrate, the first semiconductor chip and the second semiconductor chip being disposed in a form of an offset stack structure, and the second semiconductor chip including an overhang further protruding beyond a side surface of the first semiconductor chip in a first horizontal direction, an adhesive member disposed on a lower surface of the second semiconductor chip, the adhesive member including an extension extending to a lower level than an upper surface of the first semiconductor chip. The extension contacts the side surface of the first semiconductor chip, and overlaps with at least a portion of the overhang in a vertical direction.