Offset Chip-Stacked Package Layout for Heat-Driven Reliability
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Solution Overview
Problem
Chip-stacked semiconductor packages face reliability issues due to heat generation, which degrades package performance as existing designs lack effective heat dissipation mechanisms.
Innovation Solution
A chip-stacked semiconductor package design featuring offset-stacked chips with mirror-symmetrical through vias and molding layers, allowing for enhanced heat dissipation through exposed surfaces and underfill layers, improving package reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chips are stacked in a chip-stacked semiconductor package, then high capacity and miniaturization are achieved, but heat generation degrades package reliability
Solution Approach 1:
The patent segments the chip stack into multiple layers with alternating offset directions (first offset direction for odd layers, second offset direction for even layers). This segmentation allows heat to be dissipated from multiple exposed surfaces rather than being trapped in a single configuration, resolving the contradiction between high capacity stacking and heat-induced reliability degradation
Solution Approach 2:
The patent employs asymmetric offset stacking where chips in odd-numbered layers are offset in a first direction while chips in even-numbered layers are offset in a second direction opposite to the first. This asymmetric arrangement creates multiple exposed surfaces at different positions, enabling effective heat dissipation paths while maintaining high stacking density for high capacity
2Reliability
If chips are stacked in offset form to enable heat dissipation, then package reliability improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies periodic action by alternating the offset direction between adjacent layers (first offset direction for one layer, second offset direction for the next layer). This periodic pattern simplifies the manufacturing process compared to arbitrary offset arrangements, as it establishes a repeating sequence that can be systematically implemented while still achieving multiple exposed surfaces for heat dissipation
Data Source
AI summary
A chip-stacked semiconductor package includes: a base chip having a base through via; a first chip stacked on the base chip in an offset form, wherein the first chip has a first exposed surface and a first through via electrically connected to the base through via; a first molding layer positioned on the base chip and covering a first non-exposed surface, facing the first exposed surface, of the first chip; a second chip stacked on the first chip in an offset form, wherein the second chip has a second exposed surface and a second through via electrically connected to the first through via; and a second molding layer formed on the first chip and covering a second non-exposed surface, facing the second exposed surface, of the second chip.