Offset Column Stairs in 3D NAND Memory for Backside Recess Formation
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming backside recesses and metal fill-back due to limitations in column stair configurations, which affect the performance and density of memory arrays.
Innovation Solution
The proposed solution involves a three-dimensional memory device with offset column stairs and a method of manufacturing that includes forming vertically alternating sequences of insulating and sacrificial layers, patterning these layers into column stairs, and creating memory stack structures with intra-column stepped surfaces, allowing for efficient backside recess formation and metal fill-back.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional column stair configurations are used, then the structure is simpler, but the lateral etch distance is longer and backside recess formation is less efficient
Solution Approach 1:
The patent applies asymmetry by configuring column stairs with offset positions in alternating stacks. Specifically, first column stairs are positioned at different lateral locations than second column stairs, creating an asymmetric pattern that reduces lateral etch distance. This asymmetric arrangement allows etch tools to access backside recesses more efficiently while maintaining structural integrity of the memory device.
Solution Approach 2:
The patent introduces dimensional variation by arranging column stairs not only in vertical layers but also with lateral offsets across multiple alternating stacks. This multi-dimensional configuration transforms the traditional planar column stair structure into a three-dimensional offset pattern, enabling shorter lateral etch paths and improved access to backside recesses from multiple angular directions.
2Quantity of substance
If more column stairs are added to increase memory density, then storage capacity improves, but manufacturing complexity increases
Solution Approach 1:
The patent segments the column stair structure into multiple discrete alternating stacks, each containing a manageable number of column stairs. This segmentation allows the complex high-density structure to be broken down into smaller, more manufacturable units. Each alternating stack can be patterned and processed independently, reducing the overall manufacturing complexity while achieving high memory density through the aggregation of multiple segmented units.
3Productivity
If lateral etch distance is reduced to improve backside recess formation, then manufacturing efficiency improves, but column stair configuration becomes more complex
Solution Approach 1:
The asymmetric offset configuration of column stairs in alternating stacks creates shorter lateral distances between adjacent column stairs. This asymmetric arrangement optimizes the geometry for metal fill-back operations by reducing the etch tool's travel distance, thereby improving manufacturing efficiency while the systematic asymmetric pattern manages the complexity through regularity.
Data Source
AI summary
A three-dimensional NAND memory string includes an alternating stack of insulating layers and word line layers extending in a word line direction, a memory array region in the alternating stack containing memory stack structures, a group of more than two column stairs located in the alternating stack and extending in the word line direction from one side of the memory array region, and bit lines electrically contacting the vertical semiconductor channels and extending in a bit line direction which is perpendicular to the word line direction. Each column stair of the group of N column stairs has a respective step in a first vertical plane which extends in the bit line direction, and the respective steps in the first vertical plane decrease and then increase from one end column stair to another end column stair.