Offset Conductor Pillars for Stacked Semiconductor Warping Compensation

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Solution Overview

Problem

Conventional stacked semiconductor chip devices face issues with warping due to differing coefficients of thermal expansion (CTE) among various layers, leading to solder joint delamination and difficulties in establishing metallurgical bonds between interconnects, resulting in potential electrical failures.

Innovation Solution

The method involves forming semiconductor chips with conductor pillars and pads that have increasing lateral dimensions and lateral offsets towards the edges, allowing for compensation of lateral and vertical displacements caused by warping, thereby facilitating reliable interconnect bonding despite thermal expansion differences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional stacked semiconductor chips are assembled with standard conductor pads, then manufacturing is simpler, but warping causes interconnect misalignment and bonding failures

Engineering Contradiction:

Improveinterconnect bonding reliabilityVSAvoidconductor structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The conductor pillars are designed with varying lateral dimensions and offsets depending on their location on the chip. Edge and corner pillars have larger lateral dimensions and greater offsets compared to center pillars, allowing each region to compensate for the specific warping stresses it experiences during thermal cycling.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The conductor pillars are pre-positioned with lateral offsets from their corresponding pads during the fabrication process, before the chip is assembled and subjected to thermal cycling. This preliminary positioning ensures that when warping occurs during operation, the interconnects remain properly aligned for successful bonding.

Inventive Principle:

Principle #10Preliminary action

2Stability of the object's composition

If conductor pillars are positioned with lateral offsets and varying dimensions, then warping compensation is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improvechip stability under thermal cyclingVSAvoidconductor pillar positioning precision

Core Design Contradiction:

Stability of the object's compositionVSManufacturing precision

Solution Approach 1:

The invention systematically varies the lateral dimensions and positions of conductor pillars based on their location on the chip. By changing these geometric parameters in a controlled manner, the structure compensates for warping-induced misalignment without requiring ultra-precise positioning, as the design anticipates and accommodates the expected deformation.

Inventive Principle:

Principle #35Parameter changes

3Ease of manufacture

If all conductor pillars have the same lateral dimension, then manufacturing is easier, but edge interconnects fail to bond under warping conditions

Engineering Contradiction:

Improveconductor pillar fabrication easeVSAvoidedge interconnect bonding reliability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

Conductor pillars at different locations on the chip are designed with different lateral dimensions. Pillars near edges and corners have larger lateral dimensions to accommodate the greater misalignment caused by warping, while center pillars have smaller dimensions. This localized differentiation ensures reliable bonding across the entire chip surface.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively mitigates warping-induced issues by ensuring successful metallurgical bonding and maintaining electrical integrity even under thermal cycling, reducing the risk of solder joint delamination and ensuring stable interconnects across stacked semiconductor chips.

Implementation Method 1

Each of the layers of the package generally has a different coefficient of thermal expansion (CTE). In some cases, the coefficients of thermal expansion for two layers, such as the underfill material and the silicon die, may differ by a factor of ten or more. Materials with differing CTE's strain at different rates during thermal cycling.

Methodology Applied

Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS8394672B2Method of manufacturing and assembling semiconductor chips with offset pads

Publication Date: 2013.03.12 ADVANCED MICRO DEVICES INC

AI summary

A semiconductor chip device includes a first semiconductor chip adapted to be stacked with a second semiconductor chip wherein the second semiconductor chip includes a side and first and second conductor structures projecting from the side. The first semiconductor chip includes a first edge, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and that has a first lateral dimension and is adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and that has a second lateral dimension larger than the first lateral dimension and is adapted to couple to the other of the first and second conductor structures.