Offset Gate Sidewall Contacts for FinFET Wiring
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Solution Overview
Problem
The existing technologies face challenges in achieving high yield and reducing wiring congestion in logic chip block wiring, particularly in finFET logic circuits, due to bidirectional wiring requirements and irregular surface interactions, which lead to reduced chip yield and increased production costs.
Innovation Solution
The method involves forming offset gate contacts that connect directly to finFET gate sidewalls without jogs outside defined channels, allowing vias to land directly on these contacts, and filling the open offset contacts with conductive material to stitch together cut gate pairs, thereby maintaining unidirectional wiring and reducing channel blockage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If bidirectional wiring is used to connect finFET gates, then wiring flexibility is improved, but wiring congestion and channel blockage increase
Solution Approach 1:
The gate is segmented into two separate gates (first gate and second gate) that are electrically isolated from each other. This segmentation allows independent wiring connections to each gate, enabling unidirectional wiring approaches that reduce congestion while maintaining wiring flexibility. The physical separation of gates allows wiring to approach from different directions without creating complex interconnections.
Solution Approach 2:
The invention utilizes the vertical dimension by forming gates at different heights or positions along the fin structure. Offset gate sidewall contacts are formed at different vertical levels, allowing wiring to connect to gates in the vertical dimension rather than requiring horizontal wiring paths that cross channels. This dimensional transition reduces wiring congestion in the planar wiring layers.
2Reliability
If wiring channels are blocked to connect to gates, then connection reliability is improved, but chip function density decreases
Solution Approach 1:
The invention moves the connection point from the horizontal wiring plane to the vertical dimension by forming sidewall contacts on the gates. Wiring channels are not blocked because connections are made through vertical sidewall surfaces rather than requiring horizontal wiring to cross channels. This allows wiring to connect to gates without obstructing channel flow in the wiring layers, maintaining both connection reliability and chip function density.
Solution Approach 2:
The gate sidewall acts as an intermediary connection structure between the wiring and the gate electrode. Instead of requiring wiring to directly cross or block channels to reach gate contacts, the sidewall contact serves as an intermediate access point that eliminates the need for channel-blocking wiring paths, thereby maintaining channel availability for signal routing.
3Adaptability or versatility
If jogs are added to wiring paths to connect to gates, then connection flexibility is improved, but manufacturing precision requirements increase
Solution Approach 1:
The gate structure is preliminarily formed with offset sidewalls and contact regions before wiring is deposited. The sidewall contacts are pre-positioned at optimal locations that naturally align with wiring paths, eliminating the need for subsequent jog additions. This preliminary structuring of the gate with built-in alignment features simplifies the wiring process and reduces precision requirements.
Solution Approach 2:
By forming sidewall contacts in the vertical dimension, the invention eliminates the need for horizontal jogs in wiring paths. The vertical offset of sidewall contacts provides natural alignment references that simplify wiring routing, reducing the complexity and precision requirements compared to adding jogs in the horizontal plane.
Data Source
AI summary
A method of forming logic cell contacts, forming CMOS integrated circuit (IC) chips including the FETs and the IC chips. After forming replacement metal gates (RMG) on fin field effect transistor (finFET) pairs, gates are cut on selected pairs, separating PFET gates from NFET gates. An insulating plug formed between the cut gates isolates the pairs of cut gates from each other. Etching offset gate contacts at the plugs partially exposes each plug and one end of a gate sidewall at each cut gate. A second etch partially exposes cut gates. Filling the open offset contacts with conductive material, e.g., metal forms sidewall cut gate contacts and stitches said cut gate pairs together.