Offset IC Package-on-Package Stacking for Density and Testing
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Solution Overview
Problem
Current integrated circuit packaging technologies face challenges in increasing density without consuming additional space, particularly in vertically stacked configurations, which complicates testing and leads to assembly defects and increased costs.
Innovation Solution
The offset integrated circuit package-on-package stacking system involves a base substrate with contact pads, mounting active and passive components, injecting a mold cap, and singulating packages to create a configuration that allows for increased density without occupying more space, enabling individual testing and reducing assembly defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked integrated circuits are used in multi-chip packages, then integrated circuit density is improved, but testing and assembly complexity worsen
Solution Approach 1:
The patent applies preliminary action by enabling individual integrated circuit testing before packaging. The system allows die-level testing to identify known-good-die (KGD) prior to assembly, and permits post-package testing of individual circuits within the stacked configuration. This preliminary and intermediate testing capability resolves the contradiction by maintaining high density while reducing assembly complexity through defect elimination before final assembly.
Solution Approach 2:
The patent applies segmentation by treating each integrated circuit in the vertical stack as an independently testable and replaceable unit. The system enables individual circuit identification and testing within the multi-chip package, allowing selective replacement of defective die without affecting other circuits. This segmentation resolves the contradiction by maintaining high density through vertical stacking while simplifying assembly and testing through modular, independently verifiable units.
2Ease of manufacture
If conventional multi-chip packages are assembled before testing, then manufacturing process is simplified, but yield and reliability worsen
Solution Approach 1:
The patent applies preliminary action by implementing die-level testing and known-good-die (KGD) identification before the integrated circuits are packaged into multi-chip modules. This pre-packaging testing ensures that only verified functional circuits are assembled, eliminating defective units before they contribute to assembly defects. The system maintains manufacturing simplicity while improving reliability by shifting testing to occur prior to final assembly operations.
Solution Approach 2:
The patent applies feedback by implementing a testing and identification system that provides information about circuit functionality before packaging. The known-good-die (KGD) identification process creates a feedback mechanism that guides the assembly process, ensuring that only verified functional circuits are selected and assembled. This feedback loop resolves the contradiction by maintaining simple manufacturing processes while dramatically improving assembly yield through informed selection of functional components.
3Area of stationary object
If vertically stacked integrated circuits are used, then space utilization is improved, but damage risk during assembly worsens
Solution Approach 1:
The patent applies preliminary action by performing individual circuit testing and identification before the vulnerable vertical stacking assembly process. By identifying known-good-die (KGD) and verifying circuit functionality prior to stacking, the system reduces the risk of damage during assembly operations. The preliminary testing ensures that only robust, verified circuits undergo the potentially damaging vertical stacking process, thereby maintaining high space utilization while reducing damage risk.
Data Source
AI summary
An offset integrated circuit package-on-package stacking system is provided including providing a base substrate, providing an array of contact pads on the base substrate, mounting an active component and an optional passive component on the base substrate, injecting a mold cap on the base substrate, mounting an offset package on the base substrate and the mold cap, and singulating a package-on-package from the base substrate.