Offset-Stacked Semiconductor Package for Delamination Resistance
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Solution Overview
Problem
Existing semiconductor packages face challenges in enhancing reliability and durability, particularly in the connection between semiconductor chips and wiring layers, which can lead to misalignment and delamination issues.
Innovation Solution
A semiconductor package design featuring offset-stacked semiconductor chips with vertical conductive structures, a wiring layer, and a specific layer configuration that includes a passivation layer and molding layers to enhance connectivity and reduce misalignment, using materials with different bonding forces to improve adhesion and prevent delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wires and bumps are used to electrically connect semiconductor chips to PCB, then electrical connectivity is achieved, but misalignment and delamination issues occur reducing reliability
Solution Approach 1:
The patent introduces a wiring layer as an intermediary component between the semiconductor chip and the external environment. This wiring layer includes pads that are spaced apart from the molding layer with a passivation layer in between, creating a buffered connection interface that reduces direct stress and misalignment issues between the chip and PCB connections
Solution Approach 2:
The patent segments the connection structure into distinct functional layers: the semiconductor chip, vertical conductive structures, wiring layer with pads, passivation layer, and molding layer. This segmentation allows each layer to be optimized independently for its specific function, reducing the propagation of alignment errors and delamination risks across the entire structure
2Volume of moving object
If wiring layer is placed close to semiconductor chip stack for compact design, then device size is reduced, but delamination risk increases
Solution Approach 1:
The passivation layer serves as a mediator between the wiring layer and the molding layer. By placing the pad in direct contact with the vertical conductive structure and spacing it from the molding layer with the passivation layer in between, the design creates a buffered interface that maintains compact dimensions while preventing delamination through distributed stress management
Solution Approach 2:
The patent employs composite material structures with different bonding forces in the passivation layer and molding layers. These composite materials provide both mechanical support and controlled adhesion properties, allowing the wiring layer to be positioned closely to the chip stack while maintaining delamination resistance through the layered composite structure
3Reliability
If vertical conductive structures are used to connect chips to wiring layer, then connectivity is improved, but structural complexity increases
Solution Approach 1:
The patent merges multiple functions into the vertical conductive structures, which simultaneously serve as electrical connectors between the semiconductor chip and wiring layer, and as structural anchors that integrate with the molding layer. This merging reduces the need for separate components and simplifies the overall structure while maintaining improved connectivity
Data Source
AI summary
A semiconductor package may include a semiconductor chip stack including offset-stacked semiconductor chips, a wiring layer on the semiconductor chip stack, a vertical conductive structure connecting one of the semiconductor chips and the wiring layer, a molding layer at least partially covering the semiconductor chip stack and each side surface of the vertical conductive structure, and a passivation layer between the wiring layer and the molding layer. The wiring layer may include a pad in direct contact with the vertical conductive structure. The pad may be spaced apart from the molding layer with the passivation layer therebetween.