Offset Semiconductor Package Ring Structure for CTE Stress Relief
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Solution Overview
Problem
Semiconductor packages face issues of stress concentration and delamination due to coefficient of thermal expansion (CTE) mismatch and asymmetrical design, leading to mechanical and thermal stresses, especially around die corners, which can cause package warpage and detachment of solder bumps.
Innovation Solution
A semiconductor package design with a semiconductor device offset from the center axis and a cantilevered ring structure over the substrate edge, combined with a lid structure, to balance material proportions and improve bonding strength, reducing stress concentration and delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional symmetrical semiconductor package design is used, then the manufacturing process is simple, but stress concentration and delamination occur due to CTE mismatch
Solution Approach 1:
The patent applies asymmetry by offsetting the semiconductor die from the center of the substrate and creating an asymmetrical ring structure with varying thickness. The ring structure has a first thickness in a first region and a second thickness in a second region, designed to compensate for CTE mismatch between different materials. This asymmetrical configuration balances the overall package structure and reduces stress concentration, thereby improving bonding strength without excessive complexity.
Solution Approach 2:
The patent implements local quality by varying the thickness of the ring structure in different regions. The ring structure has different thicknesses (first thickness and second thickness) in different regions (first region and second region) to provide localized stress compensation. This allows targeted reinforcement where needed while maintaining overall structural balance, improving reliability without uniformly increasing complexity throughout the entire package.
2Adaptability or versatility
If materials with different CTE are used in the package, then functional requirements are met, but thermal expansion mismatch causes warpage and stress
Solution Approach 1:
The patent applies parameter changes by modifying the physical dimensions of the ring structure, specifically its thickness, to compensate for CTE mismatch. The ring structure has a first thickness in a first region and a second thickness in a second region, where these thickness parameters are specifically designed to offset thermal expansion differences between the substrate, die, and encapsulant materials. This allows the use of functionally appropriate materials while maintaining dimensional stability and reducing warpage.
Solution Approach 2:
The patent directly addresses thermal expansion by designing the asymmetrical ring structure with varying thickness to compensate for CTE mismatch between materials. The different thickness regions are calculated to counterbalance the thermal expansion forces that occur during temperature cycling, preventing package warpage and maintaining structural stability despite using materials with different thermal expansion properties.
3Ease of manufacture
If the die is positioned at the center of the substrate, then the design is symmetrical and simple, but stress concentrates at die corners causing detachment
Solution Approach 1:
The patent applies asymmetry by positioning the semiconductor die off-center on the substrate and creating an asymmetrical ring structure that corresponds to this offset position. The ring structure's varying thickness is specifically designed to compensate for the asymmetrical stress distribution that results from the off-center die placement, preventing stress concentration at die corners while maintaining manufacturing feasibility.
Solution Approach 2:
The patent implements preliminary anti-action by pre-designing the asymmetrical ring structure with compensating thickness variations before assembly. This pre-engineered structure proactively counteracts the stress concentration that would otherwise occur at die corners due to off-center positioning, preventing detachment issues before they can manifest during operation or thermal cycling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces warpage by 5-10% and stress in the adhesive layer by 25-35%, enhancing mechanical strength and reliability by minimizing CTE mismatch-induced issues.
Implementation Method 1
an adhesive layer disposed between the substrate and the ring structure
Implementation Method 2
the cover is disposed over the substrate, wherein the cover surrounds and covers the semiconductor device and includes an overhang portion cantilevered over the edge of the substrate
Data Source
AI summary
A semiconductor package includes a substrate, a first semiconductor device disposed over the substrate in an offset position toward an side of the substrate, and a ring structure disposed over the substrate and surrounding the first semiconductor device. The ring structure includes an overhang portion cantilevered over the side of the substrate.