Offset-Compensated Receiving Circuit for Differential Signal Recovery
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Solution Overview
Problem
Display devices face challenges in stably receiving data signals due to mismatched common mode voltage levels between the timing controller and the source driver, leading to signal recovery errors, especially at higher data transmission rates.
Innovation Solution
A receiving circuit with first and second capacitors, bias control circuits, and a balance compensation circuit that converts common mode voltages to specific voltage levels, removes high-frequency components, and compensates for offset voltages to produce differential signals, allowing stable signal recovery regardless of common mode voltage differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the common mode voltage level is increased to support higher data transmission rates, then the data transmission rate is improved, but the voltage level mismatch between timing controller and source driver worsens
Solution Approach 1:
The patent changes the voltage level parameter of the received signal by applying offset voltages through capacitive coupling. The first and second offset voltages shift the common mode voltage level of the differential signal to match the expected voltage level at the source driver, enabling stable signal recovery at high transmission rates without voltage level mismatch
Solution Approach 2:
The patent introduces capacitors (first and second capacitors) as intermediary elements between the timing controller and source driver. These capacitors block DC voltage levels while allowing AC signal transmission, and combined with the offset voltage generation circuit, they mediate the voltage level transition without requiring direct DC coupling between the two circuits
2Ease of operation
If capacitive coupling is used to transfer differential signals, then signal transmission is enabled, but offset voltage imbalance occurs between the two signal lines
Solution Approach 1:
The patent employs a feedback mechanism where the voltage difference between the first and second signal lines is detected and used to control the offset voltage generation circuit. When an imbalance is detected, the circuit adjusts the offset voltages to restore balance, ensuring accurate differential signal transmission
Solution Approach 2:
The patent aims to maintain equipotential conditions between the two signal lines by generating equal and opposite offset voltages. This ensures that both signal lines experience identical voltage shifts, preserving the differential nature of the signal and preventing common mode noise introduction
Data Source
AI summary
A receiving circuit includes a first capacitor connected to a first signal line, a second capacitor connected to a second signal line. A first bias control circuit may convert a common mode voltage of a first received signal provided through the first capacitor to a first voltage level to output a first biased signal. A second bias control circuit may convert a common mode voltage of a second received signal provided through the second capacitor to a second voltage level to output a second biased signal. A balance compensation circuit may receive the first biased signal and the second biased signal, compensate for an offset voltage of the first biased signal based on the second biased signal, and compensate for an offset voltage of the second biased signal based on the first biased signal to output a first differential signal and a second differential signal.