Offset Semiconductor Chip Stacking for Compact Package Design

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Solution Overview

Problem

Current semiconductor device packaging technologies face challenges in reducing the size of semiconductor packages while maintaining efficient electrical connections and structural integrity, particularly in stacking multiple semiconductor chips with varying heights and orientations.

Innovation Solution

The semiconductor device employs a configuration with two stacked bodies of semiconductor chips, each offset from the other, where columnar electrodes connect the chips and a redistribution layer ensures efficient electrical connectivity, and a resin layer seals the structure, allowing for overlapping of the stacked bodies to minimize package size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple semiconductor chips are stacked to increase capacity, then the functional integration is improved, but the package size increases

Engineering Contradiction:
Improvenumber of semiconductor chipsVSAvoidpackage size
Core Design Contradiction:
Quantity of substanceVSVolume of stationary object

Solution Approach 1:

The patent transitions from planar arrangement to three-dimensional stacking, arranging semiconductor chips in multiple layers along the thickness direction. This vertical stacking enables higher chip density without increasing the substrate area, effectively resolving the contradiction between chip quantity and package footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested arrangement where chip stacks are positioned at different horizontal locations (first stack at first location, second stack at second location) while maintaining vertical layering. This nested configuration allows multiple chips to occupy overlapping projection areas, maximizing space utilization and reducing overall package volume.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If columnar electrodes are used to connect stacked chips, then electrical connectivity is improved, but the wiring complexity increases

Engineering Contradiction:
Improveelectrical connectivityVSAvoidwiring complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the wiring function into distinct components: columnar electrodes for vertical inter-layer connections and redistribution layers for horizontal routing. This segmentation simplifies the overall wiring design by separating vertical and horizontal connectivity functions, making the complex three-dimensional wiring more manageable and reliable.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces redistribution layers as intermediary structures between columnar electrodes and chip pads. These redistribution layers act as mediators that collect signals from multiple columnar electrodes and distribute them to appropriate chip pads, simplifying the wiring architecture by providing a standardized interface layer that manages the complexity of vertical interconnections.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If chips are arranged in a single layer, then the manufacturing process is simple, but the package area is large

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidpackage area
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent extends the arrangement from two-dimensional single-layer layout to three-dimensional multi-layer stacking. By utilizing the thickness direction as an additional dimension, the patent achieves higher chip density within the same substrate area while maintaining relatively simple manufacturing processes that build upon conventional single-layer techniques.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11721672B2Semiconductor device and manufacturing method thereof
Publication Date: 2023.08.08 KIOXIA CORP
  • US11721672B2 patent drawing
  • US11721672B2 patent drawing
  • US11721672B2 patent drawing

AI summary

A semiconductor device includes a first stacked body including a plurality of first semiconductor chips stacked along a first direction, each of the first semiconductor chips being offset from the other first semiconductor chips along a second direction perpendicular to the first direction; a first columnar electrode connected to an electrode pad of the first stacked body, and extending in the first direction; a second stacked body including a plurality of second semiconductor chips stacked along the first direction, each of the second semiconductor chips being offset from the other second semiconductor chips along the second direction, the second stacked body having a height larger than the first stacked body and overlap at least a portion of the first stacked body when viewed from the top; and a second columnar electrode connected to an electrode pad of the second stacked body, and extending in the first direction.