Offset Semiconductor Die Stack Between Redistribution Structures
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Solution Overview
Problem
Fan-out semiconductor packaging is limited in scalability due to the side-by-side disposition of semiconductor dies, which restricts the integration level and number of external contacts.
Innovation Solution
A semiconductor package is designed with stacked semiconductor dies, where each die has an active and back side with conductive pillars, and is laterally encapsulated with a redistribution structure, allowing for vertical overlap and electrical connection without through silicon vias, thereby reducing manufacturing costs and susceptibility to warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If semiconductor dies are disposed side by side in fan-out semiconductor packaging, then the packaging can be manufactured with conventional processes, but the integration level and number of external contacts are limited
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side arrangement of semiconductor dies to a three-dimensional stacked configuration. Multiple semiconductor dies are vertically stacked and interconnected through conductive pillars, enabling higher integration levels by utilizing the vertical dimension. This dimensional change allows more external contacts to be achieved within a smaller footprint area.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor dies are stacked within a single package footprint. Each die is positioned vertically above another, with conductive pillars extending through the stack to establish electrical connections. This nesting approach maximizes the use of available space and increases the number of external contacts without proportionally increasing the package area.
2Reliability
If through silicon vias are used to connect stacked semiconductor dies, then electrical connection between dies is achieved, but manufacturing cost increases and susceptibility to warpage increases
Solution Approach 1:
The patent extracts and eliminates the need for through silicon vias (TSVs) by using conductive pillars that extend from the active side of each semiconductor die to connect with redistribution structures. This extraction of the TSV requirement simplifies the manufacturing process, reduces material costs, and decreases the complexity of alignment and formation processes while maintaining reliable electrical connections.
Solution Approach 2:
The patent employs conductive pillars as a cost-effective alternative to expensive TSV structures. The conductive pillars can be formed using standard semiconductor fabrication processes and are integrated directly with the die active side, eliminating the need for additional through-silicon drilling and filling operations. This approach reduces manufacturing costs while achieving the same electrical connection function.
3Reliability
If through silicon vias are used to connect stacked semiconductor dies, then electrical connection between dies is achieved, but susceptibility to warpage increases
Solution Approach 1:
The patent removes the warpage-inducing TSV structures from the design and replaces them with conductive pillars that are integrated with the die active side. This extraction eliminates the deep through-silicon holes and associated stress concentrations that cause warpage, while maintaining electrical connectivity through the conductive pillar-redistribution structure interface.
Solution Approach 2:
The patent introduces redistribution structures as intermediary elements that mediate between the conductive pillars and the external connections. These redistribution structures provide a compliant interface that can accommodate thermal expansion differences and reduce stress transmission, thereby minimizing warpage while maintaining reliable electrical connections through the conductive pillars.
Data Source
AI summary
A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first redistribution structure, a second redistribution structure, a first semiconductor die, a second semiconductor die and an encapsulant. The second redistribution structure is vertically overlapped with the first redistribution structure. The first and second semiconductor dies are located between the first and second redistribution structures, and respectively have an active side and a back side opposite to the active side, as well as a conductive pillar at the active side. The back side of the first semiconductor die is attached to the back side of the second semiconductor die. The conductive pillar of the first semiconductor die is attached to the first redistribution structure, whereas the conductive pillar of the second semiconductor die extends to the second redistribution structure.