Offset-Stacked Semiconductor Chips with Vertical Interconnectors
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Solution Overview
Problem
Existing semiconductor packages face challenges in stacking multiple chips while exposing all chip pads, particularly those disposed at both edges, due to limitations in current integration technologies and chip stacking methods.
Innovation Solution
The semiconductor package employs a method of offset-stacking semiconductor chips with redistribution layers, where each chip has pads at both edges, and vertical interconnectors are used to connect these pads, allowing for efficient exposure and connection of pads even when chips are stacked vertically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked vertically to increase integration, then the data processing capacity increases, but it becomes difficult to expose all chip pads (especially edge pads) for electrical connection
Solution Approach 1:
The patent transitions from a single-plane pad arrangement to a three-dimensional pad distribution across multiple stacking levels. Chips are offset vertically so that pads located at different heights can be accessed independently, converting a two-dimensional pad layout problem into a three-dimensional solution space where edge pads remain accessible despite vertical stacking.
Solution Approach 2:
The patent segments the chip stack into multiple offset levels, with each chip positioned at a distinct vertical offset. This segmentation allows different groups of pads (edge pads versus face pads) to be exposed at different vertical positions, enabling independent access to all pads without requiring a single large exposure area.
2Reliability
If chip pads are disposed at both edges of each chip, then the electrical connectivity is improved, but the process complexity increases due to difficulty in exposing all pads
Solution Approach 1:
The patent utilizes the vertical dimension to resolve the pad exposure problem. By offsetting chips vertically, pads that would otherwise be obscured in a planar arrangement become accessible at different heights, maintaining edge pad connectivity without increasing lateral process complexity.
3Area of stationary object
If the semiconductor package size is reduced to meet application requirements, then the package becomes more compact, but it becomes more difficult to expose all chip pads
Solution Approach 1:
The patent exploits the vertical dimension to compensate for reduced lateral package area. By distributing pads across multiple vertical levels through offset stacking, the package achieves compact lateral dimensions while maintaining full pad accessibility through the third dimension.
Solution Approach 2:
The patent implements a nested vertical structure where multiple chip layers are stacked with offsets, creating a compact overall package. Each layer is nested within the vertical envelope of the package, with pads exposed at different heights, achieving high integration density without sacrificing pad accessibility.
Data Source
AI summary
A semiconductor package may include: a first chip stack including a plurality of first semiconductor chips stacked in a vertical direction; and first vertical interconnectors electrically coupled to the plurality of first semiconductor chips, respectively, and extended in the vertical direction, wherein each of the other first semiconductor chips, except at least the uppermost first semiconductor chip from among the plurality of first semiconductor chips includes: an active surface defined by two side surfaces of the first semiconductor chip in a first direction and two side surfaces of the first semiconductor chip in a second direction crossing the first direction; a first one-side chip pad disposed at an edge of the active surface, which is close to one side surface in the first direction; a first other-side chip pad disposed at an edge of the active surface, which is close to an other side surface in the first direction; and a first redistribution pad electrically coupled to the first other-side chip pad, and disposed at an edge of the active surface, which is close to one side surface in the second direction, wherein the plurality of first semiconductor chips are stacked with an offset toward one side in a third direction crossing the first and second directions, the one side being away from the one side surface in the first direction and the one side surface in the second direction, in order to expose the first one-side chip pads and the first redistribution pads, wherein the first vertical interconnectors electrically coupled to the first semiconductor chips have one ends connected to the first one-side chip pads and the first redistribution pads, respectively.