Offset Top Die Design for Flash Memory Crack Reduction

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Solution Overview

Problem

The fragility of thin semiconductor dies in flash memory storage devices makes them prone to cracking during the encapsulation process, especially the uppermost die which lacks structural support and undergoes the least heating time, leading to potential breakage under stress.

Innovation Solution

The uppermost semiconductor die is offset along the x-axis to ensure it is supported by the die below, with the edge of the uppermost die positioned over the polyimide/passivation layer, providing additional thickness and strength against cracking, while other dies can also be offset to enhance structural integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the thickness of semiconductor dies is decreased to provide greater storage capacity in a smaller form factor, then storage capacity per unit volume is improved, but the dies become more fragile and prone to cracking during encapsulation

Engineering Contradiction:
Improvestorage capacityVSAvoiddie strength
Core Design Contradiction:
Quantity of substanceVSStrength

Solution Approach 1:

The patent offsets the uppermost die along the x-axis relative to the die below it, creating a stepped configuration. This dimensional offset allows the uppermost die to be supported by the polyimide/passivation layer of the lower die, distributing stress and preventing cracking while maintaining thin die thickness for high storage capacity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If the uppermost die is positioned directly above the die below (aligned configuration), then manufacturing simplicity is maintained, but the uppermost die is most prone to cracking due to lack of structural support

Engineering Contradiction:
Improvealignment simplicityVSAvoidcrack resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent introduces asymmetry by offsetting the uppermost die along the x-axis relative to the lower die. This asymmetric positioning creates a stepped configuration where the uppermost die extends beyond the edges of the lower die, allowing it to be supported by the polyimide/passivation layer and reducing stress concentration that would occur in a symmetric aligned configuration.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS11177241B2Semiconductor device with top die positioned to reduce die cracking
Publication Date: 2021.11.16 SANDISK TECHNOLOGIES LLC
  • US11177241B2 patent drawing
  • US11177241B2 patent drawing
  • US11177241B2 patent drawing

AI summary

A semiconductor device is disclosed including a die stack including a number of dies aligned with each other with respect to an axis, and a top die that is offset along the axis the to prevent die cracking.