Offset Vertical NAND Channels for Memory Density
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Solution Overview
Problem
Current vertical NAND channel configurations in non-volatile memory devices limit the density and efficiency of memory cells due to alignment constraints, which restricts the packing density and read/write performance.
Innovation Solution
The arrangement of vertical NAND channels in an offset configuration within select gate lines allows for closer packing and increased density, enabling more channels to be activated by a single select gate line, thereby enhancing page size and read/write performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical NAND channels are arranged in a traditional aligned configuration, then the structure is simple to manufacture, but the packing density and memory cell density are limited
Solution Approach 1:
The patent applies asymmetry by offsetting alternate vertical NAND channels from their aligned positions. Specifically, even-numbered channels are offset in a first direction while odd-numbered channels are offset in a second direction, creating an asymmetric pattern that increases packing density within the select gate line area without requiring complex manufacturing process changes
Solution Approach 2:
The patent introduces a lateral offset dimension to the traditionally vertically-aligned channel structure. By displacing channels in the lateral direction (parallel to the select gate line) rather than maintaining strict vertical alignment, the design utilizes an additional spatial dimension to achieve higher density while keeping the vertical stacking architecture intact
2Productivity
If vertical NAND channels are offset to increase packing density, then more channels can be activated by a single select gate line, but the alignment precision requirements increase
Solution Approach 1:
The patent segments the vertical NAND channels into alternating groups (even-numbered and odd-numbered channels) that are offset in opposite directions. This segmentation allows each group to be independently positioned, enabling precise control over the offset pattern and facilitating the activation of more channels by a single select gate line while maintaining manufacturability
3Quantity of substance
If channels are spaced closer together to increase density, then memory cell density improves, but interference between adjacent channels may increase
Solution Approach 1:
The asymmetric offset pattern creates alternating regions where even channels are shifted in one direction and odd channels in the opposite direction. This asymmetry distributes the lateral spacing variations throughout the structure, preventing concentrated interference zones while maintaining overall high density, as adjacent offset channels are separated by the offset distance rather than being directly adjacent
Data Source
AI summary
A non-volatile memory device can include a plurality of immediately adjacent offset vertical NAND channels that are electrically coupled to a single upper select gate line or to a single lower select gate line of the non-volatile memory device.