Top-Emission OLED Anti-Burning Wire Arrangement
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Solution Overview
Problem
Large-sized top-emission type organic light emitting display devices are prone to 'burning failure' due to short-circuits between Vss-voltage supply wires and Vdd-voltage supply wires, which can lead to heat generation, wire melting, and degradation of the display device, especially when these wires overlap and foreign substances are present.
Innovation Solution
A new arrangement of voltage supply wires with a maximum vertical space between them and the use of an anti-burning layer, an insulation layer with the same thickness as the distance between the wires, to prevent short-circuits and heat generation, ensuring a sufficient gap even with foreign substances present, thereby enhancing reliability and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Vss-voltage supply wire and Vdd-voltage supply wire are arranged without overlapping to prevent heat damage, then reliability is improved, but panel design space is insufficient and device complexity increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked arrangement by introducing different layers (first voltage supply wire on first substrate, second voltage supply wire on second substrate). This vertical separation allows wires to overlap in the planar view while maintaining sufficient physical distance through the inter-substrate spacing, thus preventing short-circuits and heat damage without increasing planar complexity.
2Area of stationary object
If Vss-voltage supply wire and Vdd-voltage supply wire overlap to save panel design space, then area utilization is improved, but risk of short-circuit and burning failure increases
Solution Approach 1:
The patent allows wires to overlap in the planar (X-Y) dimension by separating them in the vertical (Z) dimension through different substrates. The spacing between substrates provides sufficient insulation distance to prevent short-circuits even when wires overlap visually, thus achieving both compact area utilization and high reliability.
Solution Approach 2:
The patent introduces an intermediary structure (the second substrate) between the first voltage supply wire and the second voltage supply wire. This intermediary substrate acts as a physical barrier and insulator, allowing the wires to be positioned close together or overlap in the planar view while maintaining safe separation distance, thus enabling compact design without compromising reliability.
3Illumination intensity
If cathode is formed thin to improve light transmission, then luminance is improved, but electrical resistance increases and voltage drop increases
Solution Approach 1:
The patent segments the voltage supply function by providing multiple voltage supply wires (both Vss and Vdd) that extend into the display area. This segmentation allows voltage to be supplied from multiple locations rather than a single peripheral point, reducing the current path length and minimizing voltage drops across the thin cathode, thus maintaining both high light transmission and voltage uniformity.
Data Source
AI summary
A top-emission type light emitting display device and a corresponding manufacturing method are described. A device substrate has display area and non-display areas. In the display area are formed: a thin film transistor including an active layer, a gate electrode, a source electrode, and a drain electrode; and an organic light emitting element including an anode, an organic light emitting layer, and a cathode. In the non-display area a second voltage supply wire is formed on, and overlaps with, a first voltage supply wire. An anti-burning layer is disposed between the first voltage and the second voltage supply wires. The anti-burning layer is an insulation layer with the same thickness as a space sufficient to suppress burning of the wires in the overlapping region between the first voltage supply wire and the second voltage supply wire, thus improving reliability and manufacturing yield of the device.