Non-Uniform Voltage Supply Lines for OLED Array Substrates
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Solution Overview
Problem
In OLED display technology, the parasitic capacitance between voltage supply lines and node portions increases the minimum charging time for driving transistors, affecting response speed and image display quality.
Innovation Solution
The array substrate design features non-uniform voltage supply lines with specific line width variations to minimize overlapping with node portions, reducing parasitic capacitance and enhancing charging efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If voltage supply lines are designed with uniform width to ensure stable voltage supply, then voltage supply stability is improved, but parasitic capacitance with node portions increases, worsening response speed
Solution Approach 1:
The voltage supply line is designed with non-uniform width, featuring a first width in the first region and a second width in the second region. This local variation allows the line to maintain stability where needed while minimizing parasitic capacitance in critical areas, thereby improving response speed without sacrificing voltage supply stability.
Solution Approach 2:
The voltage supply line is segmented into different regions (first region and second region) with distinct width characteristics. This segmentation enables independent optimization of different portions of the line, allowing stable voltage supply in some areas while reducing parasitic effects in others, thus resolving the contradiction between stability and speed.
2Device complexity
If voltage supply lines overlap with node portions to simplify routing, then layout complexity is reduced, but parasitic capacitance increases, worsening charging time
Solution Approach 1:
The voltage supply line employs different widths in different regions to locally optimize the balance between routing simplicity and parasitic capacitance reduction. By making the line narrower in specific regions, parasitic capacitance is reduced without significantly increasing overall layout complexity.
Solution Approach 2:
The invention changes the geometric parameter (width) of the voltage supply line to control parasitic capacitance. By adjusting the width parameter in different regions, the design achieves acceptable charging times while maintaining reasonable layout complexity.
3Speed
If voltage supply lines are made narrower to reduce parasitic capacitance, then response speed is improved, but voltage supply capability deteriorates
Solution Approach 1:
The voltage supply line is designed with different widths in different regions: narrower in regions where parasitic capacitance reduction is critical for response speed, and wider in regions where voltage supply capability is paramount. This local differentiation resolves the contradiction between speed and power delivery.
Solution Approach 2:
The line is segmented into regions with different width characteristics, allowing the design to optimize for response speed in some segments while maintaining adequate voltage supply capability in others, thus balancing the trade-off between speed and power.
Data Source
AI summary
An array substrate is provided. The array substate includes a base substrate; a semiconductor material layer on the base substrate; and a plurality of voltage supply lines on a side of the semiconductor material layer away from the base substrate. In a respective subpixel, the semiconductor material layer includes an active layer of a third transistor, an active layer of a fifth transistor, an active layer of a driving transistor, and a third node portion that is connected to the active layer of the third transistor, the active layer of the fifth transistor, and the active layer of the driving transistor in the respective subpixel. At least 30% of an orthographic projection of the third node portion on the base substrate is non-overlapping with an orthographic projection of a respective voltage supply line on the base substrate.