OLED Display Clock Signal Routing via Interlayer Ground Shield
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Organic light emitting diode (OLED) displays face clock signal delay issues, which existing solutions attempt to address by using multiple flexible printed circuits (FPCs), increasing production costs and deteriorating yield.
Innovation Solution
The OLED display design includes a panel with a gate driver connected to a gate line, input line, first connecting line, second connecting line, and third connecting line, where the second connecting line does not overlap with the second electrode, reducing signal delay and eliminating the need for additional FPCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If multiple flexible printed circuits (FPCs) are provided to solve clock signal delay, then clock signal delay is reduced, but production cost increases and production yield deteriorates
Solution Approach 1:
The patent combines the clock signal transmission function with the existing FPC structure by integrating a ground layer and signal layer within the same FPC. The ground layer is formed on the FPC, and the signal layer is formed on the ground layer, creating a unified structure that transmits clock signals without requiring additional separate FPCs. This merging approach reduces production complexity and improves yield while maintaining clock signal integrity.
Solution Approach 2:
The patent introduces a ground layer as an intermediary between the signal layer and the substrate. This ground layer serves as a reference potential that shields the clock signal from interference and reduces signal delay. The ground layer is electrically connected to the substrate through grounding structures, creating an effective shield that improves signal transmission without adding external FPCs.
2Loss of time
If multiple flexible printed circuits (FPCs) are provided to solve clock signal delay, then clock signal delay is reduced, but production cost increases
Solution Approach 1:
The patent merges the clock signal transmission function into the existing FPC structure by forming a ground layer and signal layer within the same FPC. This eliminates the need for additional separate FPCs, reducing material costs and assembly complexity. The ground layer is formed on the FPC using standard deposition techniques, and the signal layer is formed on the ground layer, creating a cost-effective integrated structure.
Solution Approach 2:
The FPC structure is designed to serve multiple functions: it provides mechanical support, electrical connection, and clock signal transmission with shielding. The ground layer serves both as an electrical reference and as a shield against interference. This multi-functional design reduces the need for additional components and reduces overall production cost.
3Speed
If the first connecting line overlaps on the second electrode, then clock signal transmission is achieved, but signal interference may increase
Solution Approach 1:
The ground layer serves as an intermediary shield between the signal layer (containing the first connecting line) and the second electrode. This ground layer is electrically connected to the substrate through grounding structures, creating a reference potential that shields the clock signal from interference with the second electrode. The shield effect reduces capacitive coupling and signal interference while maintaining transmission speed.
Solution Approach 2:
The ground layer is strategically positioned beneath the signal layer in the overlapping region, providing localized shielding exactly where the first connecting line overlaps with the second electrode. This local quality approach ensures that shielding is provided only where needed, reducing interference without affecting overall signal transmission performance.
Data Source
AI summary
An organic light emitting diode display comprises: a panel including a first substrate and a second substrate facing each other; a data driver connected to a data line formed on the panel; a gate driver connected to a gate line crossing the data line in an insulated manner and formed on the panel; an input line for receiving a clock signal from the an external source; a first connecting line formed on the first substrate and electrically connected to the input line for supplying the clock signal to the gate driver; a second connecting line formed on the second substrate and electrically connected to the input line; and a third connecting line for electrically connecting the first connecting line to the second connecting line.