OLED Display Panel Layout Area Reduction via Vertical Stacking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing 3T1C pixel driver circuit in OLED display panels has a large layout area and constrained aperture ratio due to the arrangement of thin film transistors and storage capacitors with opaque metal materials, limiting the resolution and display performance.
Innovation Solution
A display panel design where the first and second thin film transistors are connected in parallel, with the storage capacitor located below the light emitting structure, allowing their projections to overlap and reducing the overall layout area, while maintaining electrical connections and optimizing the aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If thin film transistors and storage capacitors are arranged side by side with opaque metal materials, then the circuit function is achieved, but the layout area is large and aperture ratio is constrained
Solution Approach 1:
The patent applies vertical stacking to arrange components in the third dimension (Z-axis) rather than only in the plane (X-Y axis). Specifically, the storage capacitor is positioned below the light emitting structure, and transistors are stacked at different height levels, allowing their projections to overlap on the light emitting surface. This dimensional transformation reduces the lateral layout area while maintaining all necessary electrical connections through vertical vias and conductive structures.
Solution Approach 2:
The patent implements nested arrangement where the storage capacitor is located below the light emitting structure, and transistor components are positioned at different vertical levels. The projections of these components overlap on the light emitting surface, creating a nested spatial configuration that maximizes area utilization. This nesting allows multiple components to occupy the same lateral footprint while remaining electrically independent through vertical separation.
2Measurement precision
If thin film transistors and storage capacitors are arranged side by side, then the circuit function is achieved, but the resolution cannot be improved
Solution Approach 1:
By transitioning from planar to three-dimensional arrangement, the patent enables smaller lateral dimensions for each pixel while maintaining all circuit functions. The vertical stacking of transistors and capacitors frees up lateral space, allowing for higher pixel density and improved resolution without sacrificing circuit functionality.
3Illumination intensity
If thin film transistors and storage capacitors are arranged side by side, then the circuit function is achieved, but the aperture ratio is constrained leading to poor display effect
Solution Approach 1:
The vertical arrangement of components below and around the light emitting structure reduces the lateral area occupied by non-light-emitting components. This increases the aperture ratio (the ratio of light-emitting area to total pixel area) and improves display brightness and quality.
Solution Approach 2:
By nesting the storage capacitor below the light emitting structure and arranging transistors at different vertical levels with overlapping projections, the patent minimizes the lateral footprint of non-emissive components, thereby maximizing the light emitting area and improving aperture ratio.
Data Source
AI summary
A display panel and a method of manufacturing thereof are provided. The display panel includes a first thin film transistor and a second thin film transistor connected in parallel, a storage capacitor, and a light emitting structure. A projection of the first thin film transistor on a light emitting surface of the display panel overlaps with a projection of the second thin film transistor on the light emitting surface of the display panel. The storage capacitor is located below the light emitting structure, and a projection of the storage capacitor on the light emitting surface of the display panel overlaps with a projection of the light emitting structure on the light emitting surface of the display panel.