OLED Display Mask Reduction via Halftone Diffraction
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Solution Overview
Problem
The high manufacturing cost and low productivity of organic light emitting diode (OLED) displays due to the use of a large number of masks in the manufacturing process.
Innovation Solution
The OLED display is manufactured using a reduced number of masks, specifically five masks, by employing a method that includes a buffer layer, active and capacitor electrodes, gate and capacitor electrodes, interlayer insulating layers, source and drain electrodes, a bank layer, a spacer, an organic layer, and a second electrode, with the use of halftone masks and diffraction exposure techniques to form the necessary patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a large number of masks are used to form the active layer, capacitor electrodes, gate electrodes, contact holes, source and drain electrodes, via holes, first electrode, bank layer opening, and spacer, then the OLED display can be manufactured with complete structural features, but the manufacturing cost increases and productivity decreases
Solution Approach 1:
The patent combines multiple mask patterns into fewer masks by using a first halftone mask to simultaneously form the active layer pattern and capacitor electrode pattern, and a second halftone mask to simultaneously form gate electrode pattern and first electrode pattern. This merging approach reduces the total number of masks from nine to five while maintaining complete structural features.
Solution Approach 2:
The patent introduces halftone masks that utilize diffraction exposure techniques to create multiple patterns from single masks. By using halftone regions with different optical densities, the masks can form multiple structural features (such as active layer and capacitor electrodes from one mask) that traditionally required separate masks, thereby reducing mask count and improving productivity.
2Manufacturing precision
If a large number of masks are used in the manufacturing process, then all necessary patterns can be formed accurately, but the manufacturing cost increases
Solution Approach 1:
The patent merges multiple patterning functions into fewer masks by using halftone mask technology. The first halftone mask combines active layer and capacitor electrode patterning, while the second halftone mask combines gate electrode and first electrode patterning. This reduces mask quantity from nine to five, directly lowering manufacturing cost while maintaining pattern accuracy through controlled diffraction exposure.
Solution Approach 2:
The patent changes the optical parameters of the masks by using halftone regions with different optical densities. This allows single masks to create multiple pattern types with different resolutions and features by controlling the exposure parameters, thereby maintaining pattern accuracy while reducing the number of masks needed and lowering manufacturing cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the manufacturing cost and increases productivity and yield by minimizing the number of masks required, thereby improving the overall efficiency of the OLED display production process.
Implementation Method 1
the use of halftone masks and diffraction exposure techniques to form the necessary patterns
Data Source
AI summary
An organic light emitting diode (OLED) display and a method for manufacturing the same are provided. The OLED display includes a substrate, an active layer and a capacitor lower electrode positioned on the substrate, a gate insulating layer positioned on the active layer and the capacitor lower electrode, a gate electrode positioned on the gate insulating layer at a location corresponding to the active layer, a capacitor upper electrode positioned on the gate insulating layer at a location corresponding to the capacitor lower electrode, a first electrode positioned to be separated from the gate electrode and the capacitor upper electrode, an interlayer insulating layer positioned on the gate electrode, the capacitor upper electrode, and the first electrode, a source electrode and a drain electrode positioned on the interlayer insulating layer, and a bank layer positioned on the source and drain electrodes.