OLED Logic Device Merged Spacer for GIDL Reduction
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Solution Overview
Problem
Organic light emitting devices (OLEDs) face challenges with gate induced drain leakage (GIDL) due to band-to-band drain to substrate tunneling current in field depletion regions, which affects device design and efficiency.
Innovation Solution
Incorporating a dummy pattern and a merged spacer between the gate electrode and the source/drain regions of the logic device, which increases the distance between the gate electrode and the drain region, thereby reducing GIDL and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate electrode is positioned close to the drain region to reduce device area, then device area is reduced, but gate induced drain leakage (GIDL) increases due to band-to-band tunneling in the field depletion region
Solution Approach 1:
A merged spacer structure is introduced as an intermediary element between the gate electrode and the drain region. This spacer comprises a first portion adjacent to the gate electrode and a second portion adjacent to the drain region, creating a physical barrier that reduces the electric field strength in the depletion region. By mediating the interaction between gate and drain, the spacer allows close positioning while suppressing GIDL through field reduction rather than distance increase.
Solution Approach 2:
The invention changes the electrical parameters of the region between gate and drain by introducing the merged spacer with specific dielectric properties. The spacer modifies the electric field distribution and potential profile in the depletion region, altering the band-to-band tunneling conditions. By adjusting the spacer thickness and material properties, the electric field strength is reduced below the threshold for significant GIDL while maintaining compact geometry.
2Object-generated harmful factors
If the distance between gate electrode and drain region is increased to reduce GIDL, then gate induced drain leakage is reduced, but device area increases
Solution Approach 1:
The merged spacer serves as a mediator that enables GIDL suppression without requiring increased spacing. The spacer structure with its specific thickness and dielectric constant creates a controlled electric field environment that prevents excessive field strength in the depletion region, achieving harm reduction while maintaining compact device dimensions.
Solution Approach 2:
Instead of solving the GIDL problem solely through horizontal spacing (one dimension), the invention introduces a vertical dimension by stacking the merged spacer between gate and drain. This multi-dimensional approach allows compact planar footprint while using vertical thickness to control electric field strength and suppress tunneling current.
3Object-generated harmful factors
If a merged spacer is introduced to reduce GIDL by enlarging distance between gate and drain, then gate induced drain leakage is reduced, but device complexity increases
Solution Approach 1:
The merged spacer combines multiple functions into a single integrated structure: it serves as a spacing element, an electric field control layer, and a structural support feature. By merging these functions into one component rather than using separate elements, the invention reduces overall device complexity while achieving GIDL suppression through the enlarged gate-to-drain distance.
Data Source
AI summary
The present disclosure relates to an organic light emitting device including a logic device that comprises a dummy pattern and a merged spacer, and an associated fabrication method. In some embodiments, the organic light emitting device is disposed over a substrate. The logic device is coupled to the organic light emitting device, and comprises a pair of source/drain regions disposed within the substrate and separated by a channel region. A gate structure overlies the channel region and comprises a gate electrode and a dummy pattern separated from the gate electrode by a merged spacer. By arranging the dummy pattern and the merged spacer between the gate electrode and the source/drain regions, a distance between the gate electrode and the source/drain region is enlarged, and therefore reducing the gate induced drain leakage (GIDL) effect.