OLED Array Substrate Mirror Symmetry for High PPI
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Solution Overview
Problem
The existing OLED array substrate designs, such as 7T1C, 6T1C, and 6T2C layouts, limit the increase in pixels per inch (PPI) due to the layout of thin film transistors and storage capacitors, making it difficult to achieve higher pixel density and uniform image display.
Innovation Solution
The OLED array substrate incorporates a mirror symmetrical structure for driving circuits arranged in columns, where adjacent columns share reset and power signal lines and vias, reducing the number of lines and vias by half, and uses a GE1/SD1/SD2 three-layer metal line structure to facilitate a larger PPI circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 7T1C, 6T1C, or 6T2C circuit layouts are used, then current control capability is achieved, but pixel density and PPI are limited due to large circuit area
Solution Approach 1:
The patent merges the gate electrode of the driving TFT with the lower plate of the storage capacitor into a single conductive structure. This integration eliminates the need for separate gate electrode and capacitor plate structures, reducing the overall circuit area and enabling higher pixel density while maintaining the 6T1C configuration
Solution Approach 2:
The gate electrode of the driving TFT serves dual functions: as the gate electrode for transistor operation and as the lower plate of the storage capacitor. This multi-functional design reduces the number of separate components needed, simplifying the circuit layout and increasing pixel density
2Quantity of substance
If reset signal line and power signal line extend in different directions (intersecting), then signal distribution is achieved, but line density and via count increase
Solution Approach 1:
The patent adopts an asymmetric layout where the reset signal line and power signal line both extend in the same direction (horizontal direction) rather than intersecting at right angles. This asymmetric arrangement reduces the number of intersections and via connections needed, lowering line and via density while maintaining signal distribution functionality
Solution Approach 2:
The patent reorganizes the signal line routing from a two-dimensional intersecting pattern to a parallel arrangement in the same direction, effectively changing the spatial dimensionality of the signal distribution network. This reduces the complexity of interconnections and via requirements
Data Source
AI summary
An organic light-emitting diode (OLED) array substrate and an OLED display device are provided. The OLED array substrate includes a plurality of driving circuits of a plurality of sub-pixels using a mirror symmetrical structure, and a plurality of reset signal lines and a plurality of power signal lines extending along a same direction. By sharing each of the reset signal lines and each of a plurality of first vias, and sharing each of the power signal lines and each of a plurality of second vias, about half of lines of power signal lines, reset signal lines, and vias are saved. Therefore, room for increasing pixels per inch (PPI) is provided, facilitating realizing high PPI panel designs.