OLED Pixel Circuit Layout for Hydrogen Desorption in TFT Channels
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Solution Overview
Problem
The complexity of manufacturing flow and limited structure of TFTs in organic EL display devices due to the use of different materials for transistors, such as polysilicon and oxide semiconductors, results in challenges in achieving optimal transistor characteristics.
Innovation Solution
A display device configuration with a semiconductor layer, gate insulating film, and interlayer insulating films, where the drive transistor, capacitor, and connection wiring line are strategically layered and patterned to include openings that facilitate hydrogen desorption, enhancing TFT characteristics by increasing the S value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors using different materials (polysilicon and oxide semiconductor) are mounted together to achieve high drive capability, then transistor performance is improved, but manufacturing flow becomes complicated due to multiple layered structures
Solution Approach 1:
The patent applies local quality by providing different stress conditions to different regions of the same transistor structure. Specifically, a first insulating layer with compressive stress is formed in a first region, while a second insulating layer with tensile stress is formed in a second region. This allows the transistor to exhibit different characteristics in different areas, achieving high drive capability without requiring multiple different material types, thereby simplifying the manufacturing process.
Solution Approach 2:
The patent changes physical parameters (stress conditions) rather than material composition to achieve different transistor characteristics. By controlling the stress state (tensile vs. compressive) in different insulating layers, the transistor performance is optimized without introducing multiple material systems, thus avoiding the complexity associated with mounting transistors made from different materials.
2Reliability
If stress in insulating layers is controlled to improve TFT characteristics, then transistor performance is enhanced, but the structure of TFTs becomes limited due to film thickness constraints
Solution Approach 1:
The patent segments the insulating structure into multiple distinct layers, each with specific stress characteristics. Instead of relying on a single insulating layer whose stress is determined by film thickness, the structure is divided into a first insulating layer with compressive stress and a second insulating layer with tensile stress. This segmentation allows independent optimization of each layer's properties, enhancing TFT characteristics while providing structural flexibility.
Solution Approach 2:
The patent employs a composite insulating structure combining materials with different stress properties. The first insulating layer uses a material providing compressive stress, while the second insulating layer uses a material providing tensile stress. This composite approach allows the TFT structure to achieve desired stress distribution and performance characteristics without being constrained by the film thickness limitations of single-material systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves TFT characteristics by promoting hydrogen desorption, resulting in transistors suitable for various applications with controlled current supply to light-emitting elements, enabling better luminance control.
Implementation Method 1
the hole being provided at a position overlapping with a channel region of the semiconductor layer in plan view... promoting hydrogen desorption
Data Source
AI summary
A display device includes a substrate; a semiconductor layer; a gate insulating film; a gate electrode; a first interlayer insulating film; a capacitance electrode; and a second interlayer insulating film. Each of a pixel circuits includes a drive transistor, a capacitor and a connection wiring line. The capacitance electrode is provided with a first opening and a second opening in portions of positions overlapping with the gate electrode in plan view. The first interlayer insulating film and the second interlayer insulating film include a contact hole provided at a position surrounded by the first opening and a hole provided at a position surrounded by the second opening. The connection wiring line is provided on the second interlayer insulating film and is connected to the gate electrode via the contact hole. The hole overlaps with a portion of a channel region in plan view.