OLED Display Substrate Layout for IR Drop and RC Delay
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Solution Overview
Problem
High-resolution OLED displays face issues with signal delay (RC delay), voltage drop (IR drop), and voltage rise (IR rise) due to increased pixel density and parasitic resistance/capacitance, leading to color shift and non-uniform display.
Innovation Solution
The display substrate incorporates auxiliary electrode lines connected in parallel with power lines to reduce resistance, and arranges signal lines to minimize direct adjacency, reducing parasitic effects and improving display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel density is increased to achieve high-resolution display, then display resolution is improved, but parasitic resistance and capacitance increase causing signal delay and voltage drop
Solution Approach 1:
The power line is segmented into multiple sections with auxiliary electrode lines connected in parallel at different positions along the power line. This segmentation reduces the effective resistance of each segment and provides multiple parallel current paths, thereby reducing overall parasitic resistance and voltage drop while maintaining high resolution display requirements
Solution Approach 2:
The patent introduces auxiliary electrode lines that extend in the second direction (perpendicular to the primary signal line direction) to provide additional current paths. This dimensional approach creates parallel conduction paths that reduce parasitic resistance without increasing pixel density, thus maintaining signal integrity in high-resolution displays
2Area of stationary object
If signal lines are arranged closely to reduce wiring space, then device area is reduced, but parasitic capacitance between adjacent lines increases causing signal interference
Solution Approach 1:
The patent introduces auxiliary electrode lines as intermediary structures that are electrically connected to the power line but spatially separated from signal lines. These intermediary electrodes provide additional current paths while being positioned to minimize direct adjacency with signal lines, thereby reducing parasitic capacitance between power and signal lines while still reducing overall wiring resistance
Solution Approach 2:
The auxiliary electrode lines are strategically positioned in specific regions where they can effectively reduce parasitic resistance of power lines without creating excessive parasitic capacitance with signal lines. The arrangement optimizes local electrical characteristics by placing auxiliary electrodes closer to signal lines in some regions while maintaining adequate spacing in other regions
Data Source
Figure 1A~1B
Figure 1C~1E
Figure 2A
AI summary
A display substrate and a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. The sub-pixels are arranged in a sub-pixel array. At least one sub-pixel includes a first transistor, a second transistor, a third transistor and a storage capacitor. The first electrode of the third transistor is electrically connected to an active layer of the third transistor through a first via hole, and the first electrode of the third transistor is configured to be electrically connected to the light emitting element through a second via hole; the first via hole and the second via hole are at least partially overlapped with each other in a direction perpendicular to the base substrate. The display substrate can effectively reduce a voltage drop at an electrode of the light emitting element and improve the display effect.