Organic Electroluminescence Display Panel Top Gate Configuration

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Solution Overview

Problem

Current organic electroluminescence display panels face challenges with current leakage in low temperature polysilicon thin-film transistors (LTPS-TFTs) and low electron mobility in oxide-TFTs, complicating the manufacturing process with numerous masking steps required for high-performance TFTs.

Innovation Solution

The implementation of a top gate configuration for both LTPS-TFT and Oxide-TFT, where the active layers are located below the gates, allowing for the simplification of source and drain formation using a single lithography process, reducing the complexity and number of masking processes required.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If LTPS-TFT is used in the display panel, then stability is improved, but current leakage occurs

Engineering Contradiction:
ImprovestabilityVSAvoidcurrent leakage
Core Design Contradiction:
Stability of the object's compositionVSObject-generated harmful factors

Solution Approach 1:

The display panel is divided into a first region containing LTPS-TFTs and a second region containing Oxide-TFTs. This segmentation allows each transistor type to be optimized for its specific function: LTPS-TFTs provide stability in the first region, while Oxide-TFTs with low leakage characteristics handle current control in the second region, thereby resolving the current leakage problem while maintaining stability.

Inventive Principle:
Principle #1Segmentation

2Object-generated harmful factors

If Oxide-TFT is used in the display panel, then current leakage is reduced, but electron mobility is low

Engineering Contradiction:
Improvecurrent leakageVSAvoidelectron mobility
Core Design Contradiction:
Object-generated harmful factorsVSSpeed

Solution Approach 1:

Different regions of the display panel are assigned different transistor types based on local functional requirements. The first region uses LTPS-TFTs where high electron mobility is needed for switching operations, while the second region uses Oxide-TFTs where low current leakage is the priority for current control in the organic electroluminescence layer, thus optimizing performance locally in each region.

Inventive Principle:
Principle #3Local quality

3Reliability

If high-performance TFT is manufactured with multiple masking steps, then device performance is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvedevice performanceVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the formation of LTPS-TFTs and Oxide-TFTs into a unified manufacturing process flow. By integrating the fabrication steps for both transistor types and utilizing a shared planarization layer structure, the number of masking steps is reduced from the conventional eleven steps to ten steps, thereby lowering manufacturing complexity while maintaining high device performance.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11610949B2Organic electroluminescence display panel, method for manufacturing the same, and display apparatus
Publication Date: 2023.03.21 SUZHOU GOVISIONOX INNOVATION TECHNOLOGY CO LTD
  • US11610949B2 patent drawing
  • US11610949B2 patent drawing
  • US11610949B2 patent drawing

AI summary

The present disclosure discloses an organic electroluminescence display panel, a method for manufacturing the display panel, and a display apparatus. The organic electroluminescence display panel includes: a substrate including a first region and a second region adjacent to each other; a buffer layer located on the substrate; a first active layer located on the buffer layer in the first region; a first gate located on the first active layer and insulated from the first active layer; a second active layer located on the buffer layer in the second region; a metal electrode located on the first gate and insulated from the first gate; and a second gate located on the second active layer and insulated from the second active layer.