Thin-Film Omega Transistor Layout for Dense IC Routing
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Solution Overview
Problem
The increasing demand for higher functionality and speed in integrated circuits requires new devices and design flexibility, which existing technologies struggle to meet due to limitations in transistor design and manufacturing processes.
Innovation Solution
The development of a thin-film omega transistor (TFOT) with a fin-shaped gate, gate dielectric, and an oxide semiconductor layer, which can form complementary devices with FinFETs, allowing for high current transmission and optimized routing configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing transistor designs and manufacturing processes are used, then current technologies can be maintained, but the demand for higher functionality and speed cannot be met
Solution Approach 1:
The transistor is divided into two separate fins (first fin and second fin) with independent gate dielectrics and oxide semiconductor layers, allowing each fin to function as an independent current path. This segmentation enables greater design flexibility and higher functionality while maintaining manufacturability through standard fin formation processes.
Solution Approach 2:
The invention transitions from a conventional single-fin vertical structure to a dual-fin three-dimensional configuration where current flows through multiple spatial dimensions. The first and second fins are positioned adjacent to each other with source and drain regions extending between them, creating a multi-dimensional current path that increases functionality without compromising design adaptability.
2Productivity
If chip area is increased to accommodate more transistors, then functionality can be improved, but routing distances and integration efficiency may worsen
Solution Approach 1:
The first and second fins are merged into a single transistor structure sharing common source and drain regions, effectively doubling the current transmission capability within the same footprint. This merging allows more transistors to be integrated per unit area, improving integration efficiency without proportionally increasing chip area.
Solution Approach 2:
The dual-fin structure nests multiple functional elements (first gate dielectric, second gate dielectric, oxide semiconductor layers) within a compact configuration where source and drain regions are positioned between the fins. This nested arrangement maximizes the use of available space, allowing higher transistor density without excessive chip area expansion.
3Power
If saturation current is increased to meet speed requirements, then device performance improves, but manufacturing complexity increases
Solution Approach 1:
The gate dielectric thickness is varied locally between the first and second fins, with the first gate dielectric having a different thickness than the second gate dielectric. This local variation allows optimization of saturation current for each fin region while maintaining overall structural simplicity through standardized fabrication processes.
Solution Approach 2:
The transistor employs composite material structures including oxide semiconductor layers with different compositions or properties in different regions, combined with metal gate electrodes and dielectric materials. This composite approach enables high saturation current through material property optimization while keeping the structural complexity manageable through systematic material integration.
Data Source
AI summary
A method includes forming a thin-film omega transistor, which includes forming a gate fin over a dielectric layer, forming a gate dielectric on sidewalls and a top surface of the gate fin, and depositing an oxide semiconductor layer over the gate dielectric. The gate fin, the gate dielectric, and the oxide semiconductor layer collectively form a fin structure. A source region is formed to contact first sidewalls and a first top surface of a first portion of the oxide semiconductor layer. A drain region is formed to contact second sidewalls and a second top surface of a second portion of the oxide semiconductor layer.