On-Chip Debug Circuit for Asynchronous Signal Sampling
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Solution Overview
Problem
Conventional methods for testing and debugging integrated circuits are inadequate for asynchronously triggered events, as they either probe symptoms rather than root causes, require invasive techniques, or are not suitable for asynchronous signals.
Innovation Solution
A debug circuit with a triggering module, timing module, and control logic that allows for continuous and single-shot modes of operation, enabling on-chip sampling of asynchronous signals without the need for an external clock, using adjustable time bases and a multiplexer to select appropriate signals for measurement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional testing schemes use automated testers to perform test procedures and compare outputs, then testing coverage is achieved, but the ability to determine root-cause of errors is limited
Solution Approach 1:
The patent introduces an intermediary measurement system that captures intermediate signals within the device under test. This intermediary approach allows observers to see internal signal states without requiring complete system disassembly or invasive probing, thereby improving error diagnosis precision while maintaining system integrity.
Solution Approach 2:
The patent creates copies of internal signals through measurement circuits that replicate the behavior of critical internal nodes. These signal copies can be observed and analyzed externally, enabling precise error diagnosis without directly interfering with the original signal paths or requiring complex invasive testing setups.
2Ease of manufacture
If BIST circuits are used to generate inputs and check output signatures, then cost is reduced and non-invasive monitoring is achieved, but chip area is consumed and scan chains are required
Solution Approach 1:
The patent merges the measurement functionality with existing critical circuits by placing measurement circuits at nodes that are already present in the device architecture. This integration approach allows testing functionality to be added without requiring separate dedicated test circuits, thereby reducing the additional chip area consumed while maintaining ease of manufacture.
3Measurement precision
If external probes are used to directly measure signals of interest, then measurement capability is improved, but expense increases and circuit modifications are required
Solution Approach 1:
The patent introduces on-chip intermediary measurement circuits that act as mediators between the internal signals and external measurement equipment. These intermediary circuits capture and condition signals internally, allowing external probes to measure simplified versions of the signals without requiring direct access to high-speed internal nodes, thereby reducing measurement system complexity while maintaining precision.
Solution Approach 2:
The patent creates copies of internal signals through dedicated measurement circuits that replicate the signal behavior at accessible locations. These signal copies can be measured by external probes without requiring modifications to the original signal paths, reducing both the complexity of the measurement system and the invasiveness of the probing required.
4Speed
If on-chip high-bandwidth analog samplers are used to probe specific nodes, then measurement speed is improved, but synchronous clock requirement limits asynchronous signal measurement
Solution Approach 1:
The patent implements dynamic triggering mechanisms that can adapt to both synchronous and asynchronous signals. The measurement system uses configurable trigger sources that can be synchronized to clock signals when measuring synchronous circuits or operate in free-running mode for asynchronous signals, thereby maintaining high sampling bandwidth while increasing adaptability to different signal types.
Data Source
AI summary
Embodiments of an integrated circuit that includes a debug circuit are described. This debug circuit is configured to test an asynchronous circuit by performing analog measurements on asynchronous signals associated with the asynchronous circuit, and includes a triggering module configured to gate the debug circuit based on one or more of the asynchronous signals. This triggering module has a continuous mode of operation and a single-shot mode of operation. A timing module within the debug circuit has a timing range exceeding a pre-determined value, and is configured to provide signals corresponding to a first time base or signals corresponding to a second time base. Furthermore, control logic within the debug circuit is configured to select a mode of operation and a given time base for the debug circuit, which is either the first time base or the second time base.