On-Chip Functional Debugger Hierarchical Selection Tree
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Solution Overview
Problem
Current debugging methodologies for chip designs are inefficient due to poor visibility of internal nodes, leading to unsystematic debugging processes, especially in complex designs, and lack a comprehensive, real-time probing interface for functional mode debugging.
Innovation Solution
An on-chip functional debugger with a hierarchical selection tree and multiplexer-based interface that enables real-time probing of internal nodes, allowing for flexible integration and scalable debugging across various technologies and designs, without requiring additional hardware or software, and is applicable to both IP and SoC levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If JTAG interface is used for debugging, then debugging capability is provided, but debugging speed is very slow (useful only for signals in KHz frequency domain)
Solution Approach 1:
The debugging interface is segmented into multiple parallel channels (first debug channel, second debug channel, etc.) each capable of operating at high speed. This segmentation allows simultaneous debugging of multiple signals at high frequency, resolving the contradiction between debugging capability and debugging speed by providing both comprehensive coverage and high-speed operation through parallel channels.
Solution Approach 2:
The patent transitions from sequential debugging (single signal at a time) to parallel debugging by adding a temporal dimension. Multiple debug channels operate simultaneously, effectively increasing the debugging bandwidth from KHz to MHz frequency domain while maintaining comprehensive debugging capability.
2Adaptability or versatility
If Scan Chains are used for debugging, then manufacturing faults can be debugged, but functional mode debugging is not supported
Solution Approach 1:
The debugging interface is designed with universal functionality to support multiple debugging modes (manufacturing fault debugging and functional mode debugging) through a single unified architecture. The interface can be configured to debug different types of faults depending on the application requirements, providing adaptability without requiring separate specialized interfaces for each debugging mode.
3Measurement precision
If E-beam methodology is used for debugging, then detailed fault analysis is achieved, but the method is complex and costly requiring special facilities
Solution Approach 1:
The patent replaces complex physical E-beam facilities with a purely electronic/debugging-based solution. Instead of using physical electron beams to scan and analyze faults, the system uses electronic debug channels to probe and analyze signal states, achieving comparable or superior fault analysis precision without the complexity and cost of E-beam hardware infrastructure.
4Ease of operation
If Chipscope interface is used for FPGA debugging, then real time probing is not available and hardware resources are intensive
Solution Approach 1:
The debugging interface is designed to be self-service capable, providing real-time probing functionality directly through the debug channels without requiring extensive external hardware resources or complex configuration. The interface autonomously manages its own operation, enabling practical real-time debugging with minimal additional hardware overhead.
Data Source
AI summary
An on-chip functional debugger includes one or more functional blocks each providing one or more functional outputs. A hierarchical selection tree is formed by one or more selectors having the output of one of the selectors as a final output and individual selector inputs coupled either to a functional output from the functional blocks or to an output of another selector. A selection signal coupled to the select input of each of the selectors to enable a selected one of its output. An output node coupled to the final output. A method of providing on-chip functional debugging is also provided. A desired functional output from one or more available functional outputs is selected and then the selected functional output is coupled to an output node.