On-Chip Error Rate Meter for Semiconductor Die Testing
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Solution Overview
Problem
The existing methods for testing semiconductor dies require multiple hardware test equipment and criteria, leading to increased costs and time, which is undesirable in many applications.
Innovation Solution
A device with electrical self-testing capabilities, including a receiver, processor, and memory, that receives a test signal, converts it into a digital bit stream, and compares it with a reference signal to determine performance characteristics, such as bit error rate, without the need for external triggers or additional circuitry, allowing for on-chip testing and real-time metrics computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple hardware test equipment and criteria are used to test semiconductor dies, then measurement precision and reliability are improved, but device complexity and cost increase
Solution Approach 1:
The patent combines multiple test functions into a single integrated error rate meter circuit that can perform various electrical tests on semiconductor dies. The circuit includes a signal generator, signal processor, and error rate calculator all integrated into one device, eliminating the need for multiple separate test equipment while maintaining measurement precision through unified control and processing.
Solution Approach 2:
The error rate meter is designed as a universal test device capable of performing multiple test criteria and functions using a single piece of equipment. The circuit can test various performance characteristics including bit error rate, packet error rate, and other communication parameters, replacing multiple specialized test instruments with one multi-functional device.
2Measurement precision
If multiple hardware test equipment and criteria are used to test semiconductor dies, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The error rate meter enables continuous testing operations by integrating signal generation, processing, and error calculation in a single continuous workflow. The circuit processes test signals continuously without requiring interruption to change equipment or reconfigure test settings, maintaining high measurement precision while significantly reducing total testing time compared to sequential multi-equipment testing.
Solution Approach 2:
The circuit performs preliminary signal generation and processing within the same device that conducts the final error rate measurement. By pre-configuring test signals and processing capabilities within the error rate meter itself, the system eliminates time-consuming setup and transition phases between multiple external test equipment, achieving both precision and speed.
3Measurement precision
If external test equipment is used to measure bit error rate, then measurement precision is improved, but device complexity and cost increase
Solution Approach 1:
The error rate meter is designed to be self-contained with all necessary components (signal generator, processor, error calculator) integrated into a single circuit that can autonomously perform bit error rate measurements. This self-service capability eliminates dependency on external expensive test equipment while maintaining measurement precision through built-in reference signals and processing logic.
Solution Approach 2:
The circuit incorporates an on-chip copy of the reference signal generator and processing logic that mirrors the functionality of external test equipment. By replicating the essential measurement capabilities within the semiconductor die itself, the system achieves accurate bit error rate measurement without requiring costly external instrumentation.
Data Source
AI summary
An apparatus for performing an electrical test at a device is described. In one general implementation, an apparatus may include a memory, a receiver, and a processor. The receiver is configured to receive a test signal, convert the test signal into a digital test signal (bit stream) and store the digital test signal in the memory. The receiver identifies when a pre-defined number of bits of the bit stream are available in the memory. The processor is configured to perform a logic operation on the bit stream and a reference signal, generate a test result based on the logic operation, and determine whether the test result satisfies a condition. In some implementations, the processor may be configured to synchronize the digital test signal with the reference signal prior to performing of the logic operation.