On-Chip Clocked IC Testing for Pre-Packaging Speed Screening
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Solution Overview
Problem
Current integrated circuit (IC) testing methods, particularly for memory circuits, face inefficiencies due to delayed testing post-packaging and reliance on manual or automated equipment that may not test at speeds matching operational speeds, leading to limitations in detecting performance losses and parametric defects.
Innovation Solution
An integrated circuit design that includes a clocked circuit, a clock providing circuit, and a test circuit with a pad for external signals, allowing for selectable frequencies to facilitate high-speed testing through an on-chip clock circuit controlled by external testing equipment, enabling robust memory testing at or exceeding operational speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If post-packaging testing is used, then testing can be performed on encapsulated ICs, but testing is delayed and efficiency is reduced
Solution Approach 1:
The patent implements preliminary testing actions by incorporating test circuits and clock providing circuits directly into the IC design before packaging. This allows testing to be performed on the die level prior to encapsulation, eliminating the time delay associated with post-packaging testing while maintaining testing accuracy through integrated circuit-level access.
2Reliability
If automated test equipment with probe advancement is used, then testing can be performed pre-packaging, but testing speed is limited and cannot match operational speeds
Solution Approach 1:
The patent merges the clock providing function directly into the IC design, combining the clock circuit with the test circuit. This integration eliminates the speed limitations of external probe advancement equipment by enabling the IC to self-clock at its full operational speed during testing, allowing defect detection at or near operational speeds.
Solution Approach 2:
The IC design includes self-service capabilities through integrated clock providing circuits that enable the circuit to test itself at its native operational speed without requiring external equipment to advance probes or synchronize at lower speeds. The circuit provides its own timing signals, eliminating the speed bottleneck of external testing equipment.
3Reliability
If manual testing steps are used post-packaging, then testing can be performed on encapsulated ICs, but testing is slower and more prone to error
Solution Approach 1:
The patent implements self-service testing by integrating test circuits and clock providing circuits within the IC design. This automation eliminates manual testing steps entirely, as the IC performs its own testing at the die level before packaging. The integrated circuits automatically execute test sequences and evaluate results, eliminating human error and significantly improving testing efficiency while maintaining high accuracy.
Data Source
AI summary
An integrated circuit. The integrated circuit includes: (i) a clocked circuit operable in response to a clock; (ii) a clock providing circuit, coupled to clock the clocked circuit at a selectable frequency; (iii) a test circuit coupled to the clock providing circuit and the clocked circuit; and (iv) a pad configured to receive an external signal, wherein the selectable frequency is selected in response to the external signal.