On-Chip Inductor Capacitor Layout for Eddy Current Mitigation
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Solution Overview
Problem
Inductors in wireless communications circuitry occupy significant area on the substrate, making it challenging to fabricate the substrate and form other components.
Innovation Solution
Incorporating capacitors arranged in a fishbone layout on the substrate, overlapping the inductor, to minimize eddy currents and optimize inductor performance while meeting metal fill factor requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inductors are patterned onto the substrate for wireless communications circuitry, then radio-frequency signal conveyance is enabled, but the substrate area occupied by inductors becomes significant, making fabrication challenging and limiting space for other components
Solution Approach 1:
The patent combines capacitors with the inductor structure by positioning capacitor elements over the inductor's magnetic core region. This merging allows capacitors to occupy space that would otherwise be wasted, effectively utilizing the substrate area already dedicated to the inductor while providing additional useful functionality for radio-frequency signal processing.
Solution Approach 2:
The capacitor elements are nested within the spatial footprint of the inductor by positioning them over the magnetic core region. This nesting arrangement allows the capacitor to be contained within the inductor's boundary, maximizing space utilization without increasing the overall substrate area required for the wireless communications circuitry.
2Area of stationary object
If capacitors are positioned to overlap the inductor region, then metal fill factor requirements are met and substrate space is efficiently used, but eddy currents may be generated in the metallization layers
Solution Approach 1:
The capacitor structure is segmented into multiple discrete elements rather than forming a continuous conductive path. By dividing the capacitor into separate segments, the patent interrupts potential eddy current loops while maintaining the capacitive function, thus eliminating the harmful eddy currents that would otherwise be generated in the metallization layers.
Solution Approach 2:
The patent extracts or removes the continuous conductive path that would allow eddy currents to form. By positioning capacitor elements in a segmented manner over the inductor core and using insulating layers between conductive elements, the harmful eddy current pathways are taken out of the system while preserving the useful capacitive functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Minimizes eddy currents and optimizes inductor performance, allowing for efficient use of substrate space and enabling the integration of additional components without increasing the substrate's footprint.
Implementation Method 1
Arranging the capacitors in this way may serve to minimize eddy currents in the metallization layers used to form the capacitors, thereby optimizing performance of the inductor
Data Source
AI summary
An electronic device may include a transceiver with a substrate and an inductor on the substrate. A ring of ground traces may surround the inductor. Circuit components may be patterned onto the substrate overlapping the inductor, a region of the substrate surrounded by the inductor, and/or a region of the substrate between the inductor and the ring. The components may be arranged in trees with feed lines extending radially outward from a central axis. The components in each tree may be separated from the capacitors in other trees by gaps, preventing eddy currents on the trees. The components may be used to form bypass capacitors for power supply lines, a low-dropout regulator load, part of the loop filter of a phase-locked loop, or other portions of the transceiver. The components may thereby be used to convey signals while also meeting fill factor requirements associated with fabrication of the substrate.