On-Chip Inductor Layout With Tree Capacitors for Eddy Current Mitigation
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Solution Overview
Problem
Inductors in wireless communications circuitry occupy significant area on the substrate, making it challenging to fabricate the substrate and form other components.
Innovation Solution
The inductors are patterned onto a substrate with a ring of ground traces surrounding them, and capacitors are arranged in trees overlapping the inductor to minimize eddy currents, optimizing performance and meeting metal fill factor requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inductors are patterned onto the substrate with significant area, then inductor performance is improved, but substrate fabrication difficulty increases and other components cannot be formed
Solution Approach 1:
The patent transitions from planar 2D inductor layouts to 3D vertically-stacked inductor structures. Multiple inductor windings are stacked along the vertical dimension (z-axis) with interleaved conductive traces on different substrate layers, enabling compact high-performance inductors that do not occupy excessive substrate area and allow other components to be fabricated nearby.
Solution Approach 2:
The patent implements nested inductor structures where inner windings are positioned within the magnetic field region of outer windings. The conductive traces are interleaved and nested across multiple substrate layers, with ground traces and signal traces alternating in a nested pattern that optimizes magnetic coupling and reduces parasitic effects.
2Quantity of substance
If capacitors are arranged in trees overlapping the inductor, then metal fill factor requirements are met, but eddy currents are generated that degrade performance
Solution Approach 1:
The patent segments the capacitor structure into multiple disconnected radial branches extending from the central axis, similar to a fishbone layout. These segmented capacitor branches are distributed around the inductor perimeter, providing sufficient metal fill factor while breaking up continuous conductive paths that would otherwise support harmful eddy currents.
Solution Approach 2:
The patent applies different structural characteristics to different regions: capacitor branches are positioned in regions where they provide fill factor without creating large loop areas, while gaps are strategically placed to interrupt eddy current paths. The local arrangement of capacitor traces is optimized to balance fill factor requirements with eddy current mitigation in each specific region around the inductor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes eddy currents and optimizes inductor performance while meeting fabrication requirements, allowing for efficient use of substrate space.
Implementation Method 1
an inductor layered on the substrate and extending around a first region of the substrate
Implementation Method 2
a ring of ground traces on the substrate and extending around the inductor and a second region of the substrate, the ring of ground traces being laterally separated from the inductor by the second region of the substrate
Data Source
AI summary
An electronic device may include a transceiver with a substrate and an inductor on the substrate. A ring of ground traces may surround the inductor. Circuit components may be patterned onto the substrate overlapping the inductor, a region of the substrate surrounded by the inductor, and/or a region of the substrate between the inductor and the ring. The components may be arranged in trees with feed lines extending radially outward from a central axis. The components in each tree may be separated from the capacitors in other trees by gaps, preventing eddy currents on the trees. The components may be used to form bypass capacitors for power supply lines, a low-dropout regulator load, part of the loop filter of a phase-locked loop, or other portions of the transceiver. The components may thereby be used to convey signals while also meeting fill factor requirements associated with fabrication of the substrate.