On-Chip Slice Buffer Processing for Lower Video Memory Latency
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Solution Overview
Problem
The large size of frame data in video image processing causes memory access delays and extended AI reasoning time due to the need for interaction with external storage units, leading to inefficiencies in frame-based data processing.
Innovation Solution
Implementing a chip with a first processor and a slice buffer connected to a second processor, where the first processor writes slice data into the buffer and sends an interrupt signal, allowing the second processor to read and process the slice data independently, reducing reliance on external memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If frame-based data processing is used, then complete image processing can be achieved, but memory access delays and extended processing time occur due to large data size
Solution Approach 1:
The patent divides a complete image frame into multiple slice data units (e.g., 8 slices per frame). Each slice can be independently processed by the second processor after being written by the first processor, eliminating the need to wait for complete frame assembly. This segmentation reduces memory access delays and enables parallel processing, directly improving productivity while reducing time loss.
2Productivity
If frame-based data processing is used, then complete image processing can be achieved, but power consumption increases due to frequent external memory access
Solution Approach 1:
By segmenting frame data into slices that fit within on-chip buffer capacity, the system minimizes external memory access frequency. The first processor writes slices to the buffer, and the second processor reads and processes them independently, reducing the energy-intensive external memory interactions while maintaining processing efficiency.
Solution Approach 2:
The on-chip buffer acts as an intermediary between the first processor and second processor, and between the chip and external memory. It stores slice data locally, enabling the second processor to read and process data without frequent external memory access, thereby reducing power consumption while maintaining productivity.
3Loss of time
If slice-based processing is implemented, then memory access delay is reduced, but device complexity increases due to additional buffer and interrupt mechanisms
Solution Approach 1:
The on-chip buffer serves multiple functions: it stores slice data from the first processor, provides data to the second processor for independent processing, and enables interrupt-based synchronization. This multi-functionality reduces the need for separate dedicated components, minimizing the increase in device complexity while achieving reduced memory access delay.
Solution Approach 2:
The system implements self-service through automatic interrupt generation. When the first processor writes slice data to the buffer, it automatically generates an interrupt signal to notify the second processor, eliminating the need for complex polling or centralized control mechanisms. This reduces device complexity while enabling timely data processing.
Data Source
AI summary
A chip includes a first processor, a slice buffer and a second processor. An output of the first processor is connected to an input of the slice buffer and an input of the second processor respectively. An output of the slice buffer is connected to the input of the second processor. The first processor is configured to write slice data into the slice buffer after the slice data has been processed, and transmit an interrupt signal to the second processor. The second processor being configured to read the slice data from the slice buffer based on the interrupt signal, and process the slice data to obtain corresponding result data.