On-Chip Variation Determination Using Adjustable Delay Chains
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Solution Overview
Problem
As semiconductor technology scales down, on-chip variations deviating from Static Timing Analysis (STA) models become significant, necessitating a method for intrinsic variation determination in semiconductor processes to ensure accurate timing signoff and manufacturing.
Innovation Solution
An integrated circuit with a delay determination circuit and control circuit, including launch and capture registers, and adjustable delay elements, which output and capture test data to determine path delays under various Process, Voltage, and Temperature (PVT) conditions, allowing for on-chip variation measurement and correlation with STA models.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Static Timing Analysis (STA) is used for timing computation, then timing analysis can be performed efficiently without fabrication, but on-chip variations deviating from STA models become significant as technology scales down
Solution Approach 1:
The patent applies preliminary action by incorporating delay determination circuits and calibration structures into the IC design phase. These circuits pre-characterize timing paths and store calibration data that can be used later to correct STA inaccuracies, allowing variation compensation before actual manufacturing and testing.
Solution Approach 2:
The patent implements feedback mechanisms where actual timing measurements from delay determination circuits are compared against STA predictions. The differences are used to generate correction factors or calibration data that feed back into the timing analysis process, continuously improving accuracy between STA models and actual on-chip behavior.
2Measurement precision
If on-chip variation determination circuits are added to measure intrinsic variations, then timing accuracy improves, but device complexity increases
Solution Approach 1:
The patent merges delay determination circuits with existing logic paths and register structures. By integrating these measurement functions into the normal circuit fabric rather than adding completely separate test structures, the patent reduces overall complexity while still achieving accurate variation measurement.
Solution Approach 2:
The delay determination circuits are designed to serve multiple functions: they characterize timing variations, provide calibration data for STA, and can be used for both design-stage analysis and post-fabrication verification. This multi-functionality reduces the need for separate dedicated structures for each purpose.
3Reliability
If delay elements are made adjustable to determine path delays under various PVT conditions, then timing model accuracy improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses parameter changes by varying delay element characteristics (such as transistor width, length, or threshold voltage) to create delay chains that span the expected range of PVT variations. This allows the circuits to self-calibrate across different process, voltage, and temperature conditions without requiring external adjustment mechanisms.
Data Source
AI summary
A method for providing an on-chip variation determination and an integrated circuit utilizing the same are provided. The method includes: outputting, by a launch register circuit, a test data to the capture register circuit according to the first clock; receiving, by a capture register circuit, the test data from the launch register circuit according to the second clock; adjusting, by a control circuit, a first number of a first chain of delay elements to generate the first clock and a second number of a second chain of delay elements for the capture register circuit to just capture the test data to generate the second clock; and determining, by the control circuit, a path delay between the launch register circuit and the capture register circuit based on the first number of the first chain of delay elements and the second number of the second chain of delay elements.