On-Die Termination Calibration Using Sequential Code Comparison
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Solution Overview
Problem
Conventional on-die termination calibration for semiconductor integrated circuits is hindered by long calibration times and the inability to perform normal calibration within the refresh cycle time tRFC, leading to potential omission of calibration operations and adverse effects on circuit performance due to voltage and temperature changes.
Innovation Solution
An apparatus and method that includes a comparing unit for sequential comparison of code conversion voltage with a reference voltage, a code control unit to determine level changes, and counters to adjust internal codes, allowing for reduced calibration time and flexible adjustment of on-die termination resistance values without being restricted by the refresh cycle time tRFC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional on-die termination calibration is performed using traditional methods, then calibration accuracy can be achieved, but calibration time becomes excessively long and exceeds the refresh cycle time tRFC
Solution Approach 1:
The calibration process is segmented into two distinct phases: initial calibration performed during system stabilization, and normal calibration performed during refresh operations. This segmentation allows each calibration type to be optimized independently, with normal calibration being streamlined to complete within the refresh cycle time tRFC while maintaining accuracy through the stored reference voltage.
2Reliability
If calibration operations are performed frequently to maintain accuracy under voltage and temperature changes, then circuit performance is maintained, but power consumption increases
Solution Approach 1:
Calibration is performed periodically during regular refresh operations rather than continuously. The stored reference voltage in the capacitor allows the system to maintain calibration accuracy through periodic updates synchronized with the refresh cycle, reducing power consumption while ensuring circuit performance is maintained under varying voltage and temperature conditions.
3Measurement precision
If traditional calibration methods are used, then comprehensive calibration can be performed, but the calibration process cannot be completed within the refresh cycle time tRFC
Solution Approach 1:
The reference voltage is preliminarily established during the initial calibration phase and stored in a capacitor. This preliminary action allows subsequent normal calibration operations to be performed quickly by comparing against the pre-stored reference voltage, enabling complete calibration to be finished within the refresh cycle time tRFC.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces calibration time, enables normal calibration operations within the refresh cycle time, and minimizes power consumption by ensuring calibration is performed within the offset margin, thus maintaining circuit performance and simplifying the circuit structure.
Implementation Method 1
a comparing unit for comparing a code conversion voltage, obtained by converting an internal code into an analog voltage, with a reference voltage to generate a comparison result signal
Implementation Method 2
The driver leg 20 has a structure that functions as an analog/digital converter, and distributes a power supply voltage with a distribution ratio between resistance selected according to an internal code 'P' and external resistance RQ and outputs a code conversion voltage (zq)
Data Source
AI summary
An apparatus for calibrating on-die termination for a semiconductor integrated circuit includes a comparing unit that compares a code conversion voltage, which is obtained by converting an internal code into an analog voltage, with a reference voltage, and outputs a comparison result signal, a code control unit that compares a current comparison result signal and a previous comparison result signal, among comparison result signals obtained by sequential comparison operations by the comparing unit, to determine whether or not the levels thereof are the same, and outputs an external code update signal according to the comparison result, and a counter that increases or decreases the internal code according to the comparison result signal and outputs the internal code as an external code according to the external code update signal.