On-Die ECC Engine Testing with Decoupled Memory Arrays
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Solution Overview
Problem
The increasing bit errors and decreasing yield in DRAMs due to shrinking fabrication design rules necessitate improved reliability and test coverage in semiconductor memory devices.
Innovation Solution
Incorporation of an on-die error correction code (ECC) engine with latches and a control logic circuit that allows for a test mode where the connection with the memory cell array is cut off, enabling ECC decoding on test data with injected error bits, and providing a severity signal indicating error correction capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the connection between the ECC engine and the memory cell array is maintained during testing, then the memory cell array can be tested, but the ECC engine cannot be tested independently with various error patterns
Solution Approach 1:
The patent segments the testing functionality by introducing a test mode that decouples the ECC engine from the memory cell array. The ECC engine can be tested independently using latches (first latch for test data, second latch for test parity data) without requiring the memory cell array, allowing comprehensive ECC testing with various error patterns while maintaining separate testing paths for different components
2Reliability
If the parity check matrix is disclosed during ECC engine testing, then the testing can be performed, but the security and proprietary information of the memory device is compromised
Solution Approach 1:
The patent uses copying by creating test data and test parity data in latches that replicate the normal ECC operation without requiring the actual memory cell array. The ECC engine processes these copied test patterns internally, allowing functionality verification while the proprietary parity check matrix remains hidden within the device and is never exposed to external testing equipment
3Reliability
If traditional testing methods are used without a test mode, then the device structure remains simple, but the test coverage and reliability assessment are insufficient
Solution Approach 1:
The patent implements multi-functionality by designing the ECC engine to handle both normal memory operations and test operations through a unified structure. The same ECC decoding logic processes both actual memory data and test data, while the control logic circuit selectively activates test mode based on mode register settings, allowing comprehensive testing without duplicating the entire ECC engine structure
Data Source
AI summary
A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine and a control logic circuit. The on-die ECC engine includes a first latch and a second latch. The control logic circuit sets the semiconductor memory device to a test mode in response to a first mode register set command. The on-die ECC engine, in the test mode, cuts off a connection with the memory cell array, receives a test data, stores the test data in the first latch, performs an ECC decoding on the test data stored in the first latch and a test parity data, stored in the second latch in response to a read command and provides an external device with a severity signal indicating whether the test data and the test parity data includes at least one error bit and the at least one error bit is correctable.