On-Die Termination Control for Memory Test Compatibility
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Solution Overview
Problem
Conventional semiconductor memory devices with on-die termination circuits face challenges in impedance mismatching due to variations in manufacturing processes, supply voltage, and operation temperature, leading to signal distortion and malfunction, especially during high-speed data transmission and test operations, requiring additional pins for termination-off signals.
Innovation Solution
A semiconductor memory device design that inactivates the on-die termination circuit using a combination of signals from the boundary scan test, such as the boundary-test entry signal, shift signal, and output control signal, without requiring additional pins, by generating an initializing signal and driving clocks to produce a termination-off signal, allowing the termination resistance to be controlled through a mode register setting value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an additional pin is added to turn off the on-die termination circuit during test operations, then test device compatibility is improved, but device complexity increases
Solution Approach 1:
The existing input pins are made multi-functional by configuring them to serve both normal operation functions and test operation functions. The control signal generator detects test mode through specific signal combinations on existing pins and automatically configures the on-die termination circuit accordingly, eliminating the need for dedicated test pins while maintaining full test device compatibility
Solution Approach 2:
The functions of normal operation control and test operation control are merged into a single control mechanism. The control signal generator integrates both operation modes and uses the same input pins for both modes, combining what were previously separate control paths into one unified system that automatically switches between modes based on detected signal patterns
2Reliability
If the on-die termination circuit is activated to match impedance, then signal transmission quality is improved, but test operations with multiple test devices fail due to drivability decline
Solution Approach 1:
The on-die termination circuit is made dynamically controllable, switching between activated and inactivated states based on the operational mode. During normal operation, the circuit is activated to ensure impedance matching and signal quality. During test operations, the circuit is automatically inactivated to maintain compatibility with multiple test devices having different drivabilities, with the transition controlled by the control signal generator detecting test mode signals
3Adaptability or versatility
If the on-die termination circuit is inactivated during test operations, then test device compatibility is improved, but signal transmission quality deteriorates during normal operation
Solution Approach 1:
The control signal generator dynamically controls the termination circuit state based on detected operational mode. In normal operation mode, the circuit remains activated to maintain impedance matching and signal quality. In test operation mode, the circuit is inactivated to ensure compatibility with test devices, with automatic mode detection and switching implemented by the control signal generator
Data Source
AI summary
A semiconductor memory device is able to inactivate an on-die termination circuit without an additional pin. The semiconductor memory device includes a control signal generator, a resistance control unit, and a resistance supply unit. The control signal generator generates an initializing signal and driving clocks in response to a plurality of control signals. The resistance control unit, initialized by the initializing signal, generates a termination-off signal in response to the driving clocks. The resistance supply unit supplies termination resistance in response to the termination-off signal and a mode register setting value. The plurality of control signals are inputted through input pins not connected to the resistance supply unit.