On-Package Memory Interconnect Layout for Reduced Package Thickness
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Solution Overview
Problem
The integration of on-package memory architectures in IC packages results in significant thickness disparities between memory and processor components, leading to challenges in heat dissipation and increased complexity due to uneven heights, which are addressed by eliminating the memory package substrate and BGA balls, thereby reducing overall thickness and improving efficiency.
Innovation Solution
The on-package memory architecture eliminates the memory package substrate and BGA balls, using a direct connection of memory dies to the main package substrate through metal stubs and a planar heat spreader, reducing thickness and enhancing heat dissipation by minimizing signal routing length and eliminating the need for complex heat spreader designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated memory package substrate with ball grid array is used, then electrical interconnection is achieved, but thickness increases and manufacturing complexity increases
Solution Approach 1:
The patent extracts and eliminates the dedicated memory package substrate and ball grid array from the traditional on-package memory architecture. By removing these intermediate components, the memory die is directly coupled to the processor die, significantly reducing the overall thickness while maintaining electrical interconnection functionality through direct bonding interfaces.
Solution Approach 2:
The patent merges the memory package substrate functions directly into the processor die substrate. Instead of having separate memory and processor packages, the memory die is integrated directly onto the processor package substrate, eliminating the need for intermediate memory package substrates and reducing overall system thickness.
2Reliability
If a dedicated memory package substrate with ball grid array is used, then electrical interconnection is achieved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the dedicated memory package substrate and ball grid array from the traditional on-package memory architecture. By removing these intermediate components, the memory die is directly coupled to the processor die, significantly reducing the overall thickness while maintaining electrical interconnection functionality through direct bonding interfaces.
Solution Approach 2:
The patent merges the memory package substrate functions directly into the processor die substrate. Instead of having separate memory and processor packages, the memory die is integrated directly onto the processor package substrate, eliminating the need for intermediate memory package substrates and reducing overall system thickness.
3Temperature
If non-planar heat spreaders are used to accommodate thickness disparity, then heat dissipation is addressed, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the dedicated memory package substrate and ball grid array from the traditional on-package memory architecture. By removing these intermediate components, the memory die is directly coupled to the processor die, significantly reducing the overall thickness while maintaining electrical interconnection functionality through direct bonding interfaces.
Data Source
AI summary
Methods and apparatus to reduce thickness of on-package memory architectures are disclosed. An on-package memory architecture includes a memory die; a bonding pad including a first surface and a second surface opposite the first surface; a wire bond electrically coupling the memory die to the first surface of the bonding pad; and a metal stub protruding from the second surface of the bonding pad. The metal stub is to electrically couple with a contact pad on a package substrate of an integrated circuit (IC) package.