On-Pitch Drain Select Gate Electrodes for 3D Memory Leakage Reduction
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Solution Overview
Problem
Three-dimensional memory devices face challenges in reducing leakage currents caused by peripheral dummy structures, which increase device density but also lead to pattern distortion and higher leakage current frequencies.
Innovation Solution
The implementation of on-pitch select gate electrodes with the same periodicity as memory stack structures, which reduces or eliminates leakage currents by optimizing the arrangement and isolation of drain-select-level assemblies and isolation strips in the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device density is increased by adding more memory structures, then storage capacity is improved, but leakage current increases due to peripheral dummy structures
Solution Approach 1:
The patent removes peripheral dummy structures from the memory device perimeter. By extracting these harmful dummy structures that cause leakage current, the device maintains high density from functional memory structures while eliminating the source of leakage at the boundaries.
Solution Approach 2:
Instead of adding dummy structures to fill peripheral spaces (conventional approach), the patent inverts the approach by intentionally leaving peripheral regions empty or filled with isolation material only. This inversion eliminates the pattern distortion and leakage current associated with traditional dummy structure filling.
2Object-generated harmful factors
If on-pitch select gate electrodes are implemented with same periodicity as memory stacks, then leakage current is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges the periodicity of select gate electrodes with the periodicity of memory stack structures. By aligning their spatial arrangements and pitch dimensions, the fabrication processes for both structures can be integrated, reducing the number of separate lithography and etching steps required.
Solution Approach 2:
The select gate electrodes serve dual functions: they provide electrical selectivity for memory operations and simultaneously act as structural templates that define the periodic arrangement of memory stacks. This multi-functionality simplifies the overall device architecture and manufacturing process.
Data Source
AI summary
An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers. The drain-select-level assemblies may be provided by forming drain-select-level openings through a drain-select-level sacrificial material layer, and by forming a combination of a cylindrical electrode portion and a first gate dielectric mayin each first drain-select-level opening while forming a second gate dielectric directly on a sidewall of each second drain-select-level opening in a second subset of the drain-select-level openings. A strip electrode portion is formed by replacing the drain-select-level sacrificial material layer with a conductive material. Structures filling the second subset of the drain-select-level openings may be used as dummy structures at a periphery of an array. The dummy structures are free of gate electrodes and thus prevents a leakage current therethrough.