On-the-Fly Decryption Integrated Circuit Zero Latency
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Solution Overview
Problem
Existing integrated circuit systems face latency issues during real-time decryption of encrypted software images stored in external memory, which degrades system performance and security.
Innovation Solution
A counter-mode decryption system within the integrated circuit generates encrypted counter values using addresses and a secret key, allowing for zero additional cycles of latency by pre-generating these values during code retrieval, utilizing an XOR logic block for decryption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If real-time decryption is performed during code retrieval from external memory, then security is improved, but system latency increases and performance degrades
Solution Approach 1:
The patent pre-generates encrypted counter values using addresses while the encrypted code is being obtained from external memory, before the decryption is actually needed. This preliminary generation of decryption keys eliminates wait time during the decryption process, maintaining security while avoiding latency penalties in the critical path.
Solution Approach 2:
The decryption process is segmented into two independent parts: (1) pre-generation of encrypted counter values using addresses, and (2) final decryption using XOR operation. This segmentation allows the time-consuming cryptographic operations to be performed in parallel with code retrieval, rather than sequentially, reducing overall system latency.
2Reliability
If AES decryption engine processes code in real-time during external memory access, then security protection is maintained, but system performance is degraded due to additional processing time
Solution Approach 1:
The patent extracts the time-consuming cryptographic processing out of the critical code execution path by pre-generating encrypted counter values during memory access. This separates security processing from performance-critical operations, maintaining security protection while eliminating its negative impact on system performance.
Solution Approach 2:
The patent introduces an intermediary mechanism (encrypted counter values generated from addresses) that mediates between the security requirement and performance constraint. This intermediary allows decryption to occur without blocking the main execution flow, as the counter values are prepared in advance and applied through efficient XOR operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables direct execute-in-place processing of encrypted code with zero additional latency, enhancing security and system performance without degrading overall system performance.
Implementation Method 1
an exclusive-OR logic block having the encrypted code and the encrypted counter value as inputs and having decrypted code as an output
Data Source
AI summary
Methods and systems are disclosed for on-the-fly decryption within an integrated circuit that adds zero additional cycles of latency within the overall decryption system performance. A decryption system within a processing system integrated circuit generates an encrypted counter value using an address while encrypted code associated with an encrypted software image is being obtained from an external memory using the address. The decryption system then uses the encrypted counter value to decrypt the encrypted code and to output decrypted code that can be further processed. A secret key and an encryption engine can be used to generate the encrypted counter value, and an exclusive-OR logic block can process the encrypted counter value and the encrypted code to generate the decrypted code. By pre-generating the encrypted counter value, additional cycle latency is avoided. Other similar data independent encryption/decryption techniques can also be used such as output feedback encryption/decryption modes.