Onboard Storage Controller Segmentation for Data Access Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional computing systems face performance lag due to latency in data storage and access, particularly with mechanical disk systems and networked architectures, and have not proportionally increased cache memory as storage capacity grows, leading to a lower cache hit ratio and increased costs for adding main memory.
Innovation Solution
Integration of a data storage controller with memory controller functions on a host computing system, utilizing a multi-channel data storage and caching architecture that includes solid-state memory modules and remote disk units, allowing for faster data access and caching without significant cost increases, by eliminating bus and network contentions and optimizing storage and caching resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data storage capacity is increased using external storage disks, then storage capacity is improved, but data access speed deteriorates due to latency from bus contentions and network bottlenecks
Solution Approach 1:
The patent segments the storage system into multiple independent channels, each with its own controller and storage devices. This segmentation allows parallel data access through multiple pathways, reducing bus contention and improving data access speed while maintaining high storage capacity.
Solution Approach 2:
The patent introduces an onboard storage controller as an intermediary between the CPU and external storage disks. This controller caches frequently accessed data in onboard memory, mediating between the fast CPU and slow external storage to improve data access speed without sacrificing storage capacity.
2Speed
If cache memory capacity is increased to improve cache hit ratio, then data access speed is improved, but system cost increases due to expensive RAM
Solution Approach 1:
The patent replaces the traditional mechanical approach of using expensive RAM for caching with a hybrid system that uses onboard memory controllers and solid-state storage devices. This substitution provides caching functionality at lower cost while maintaining improved data access speed.
Solution Approach 2:
The patent changes the physical state and location of cache memory from traditional system RAM to onboard memory controllers and solid-state devices. This parameter change enables larger cache capacity at reduced cost while maintaining the performance benefits of fast data access.
3Quantity of substance
If more main memory is added to improve caching capability, then cache capacity is improved, but system cost increases due to higher RAM expenses
Solution Approach 1:
The patent creates a multi-functional onboard storage controller that serves both as a cache management unit and a storage interface controller. This universal component provides both caching and storage access functions, increasing cache capacity without the need for additional expensive RAM.
4Quantity of substance
If data storage controller is external to the host system, then storage capacity is improved, but data access latency increases due to cabled architecture
Solution Approach 1:
The patent merges the storage controller with the host system's onboard memory controllers, creating an integrated storage management unit. This combination eliminates the need for separate cabled connections and reduces data access latency while maintaining high storage capacity through external disk connections.
Data Source
AI summary
A controller and memory unit for a host computer has a primary controller coupled to a parallel bus interface connectable or connected to the host computer, and by cable connections to one or more remote memory disk units, one or more secondary controllers coupled by parallel bus to the primary controller, and one or more solid-state memory modules coupled by parallel bus one-to-one with the secondary controllers. The primary controller provides read/write access to the remote memory disk units and read/write access to each of the solid-state memory modules through the associated secondary controller.