On-Chip I/O Compare Logic for Fast Fail-Safe Verification
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Solution Overview
Problem
Existing microcontroller units (MCUs) and integrated circuits used in functional safety applications rely on external circuits for signal failure detection, which is costly and delays detection time, failing to provide adequate fault coverage and compliance with stringent safety standards like ISO26262 and IEC61508.
Innovation Solution
A packaged IC chip with on-chip monitoring capabilities that includes comparison logic to verify output signals against redundant or duplicate signals, allowing for deterministic failure detection and increased fault coverage, utilizing either hardware or Configurable Logic Blocks (CLBs) for comprehensive verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external circuits are used for signal failure detection, then detection capability is provided, but cost increases and detection time is delayed
Solution Approach 1:
The patent merges the failure detection function with the existing I/O interface circuitry by integrating a comparison logic unit within the same chip. The comparison logic is coupled to receive both the output signal from the control peripheral and a comparison signal, performing failure detection internally rather than requiring separate external circuits. This integration eliminates the time delay associated with external signal transmission and reduces overall system cost.
Solution Approach 2:
The patent introduces a comparison logic unit as an intermediary component that receives the output signal and compares it with a comparison signal (which may be an inverted version or redundant signal). This intermediary performs the failure detection function internally, acting as a mediator between the control peripheral and the external world, thereby enabling fast detection without requiring external circuits.
2Reliability
If external circuits are used for signal failure detection, then failure detection is achieved, but system cost increases
Solution Approach 1:
The patent combines multiple functions (I/O signal generation, signal comparison, and failure detection) into a single integrated circuit chip. The comparison logic unit is implemented using standard logic gates (such as XOR gates) that can be fabricated using the same process as the rest of the I/O interface, eliminating the need for separate external detection circuits and reducing overall system cost.
Solution Approach 2:
The comparison logic unit serves multiple purposes: it compares the output signal with the comparison signal for failure detection, can operate in different modes (e.g., comparing with inverted signal or redundant signal), and integrates with the existing I/O peripheral structure. This multi-functionality reduces the need for additional dedicated components, thereby lowering system cost.
3Loss of time
If on-chip comparison logic is implemented, then detection time is reduced, but chip complexity increases
Solution Approach 1:
The patent segments the failure detection function into a dedicated comparison logic unit that is distinct from but coupled to the control peripheral. This segmentation allows the comparison operation to be performed independently and in parallel with other I/O operations, reducing detection time while keeping the added complexity localized and manageable within the chip architecture.
Data Source
AI summary
A packaged integrated circuit (IC) chip that provides input/output (I/O) signal fail safe verification is disclosed. The packaged IC chip includes a first processing unit, a first control peripheral coupled to receive a first processed signal from the processing unit and to provide an output signal, and compare logic. The compare logic is coupled to receive the output signal and a comparison signal, to compare the output signal and the comparison signal, and to provide an error signal responsive to a difference between the output signal and the comparison signal.