On-Die Memory Termination Switching for Impedance Matching
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Solution Overview
Problem
High-speed signaling systems face sub-optimal performance due to impedance discontinuity and signal attenuation issues in single-termination schemes, leading to reduced signaling margins and increased error rates.
Innovation Solution
Implementing multiple, graduated on-die termination structures per high-speed signaling line, allowing for switchable selection between high-load and low-load terminations based on whether the memory module is the destination for incoming signals, to match transmission line impedance and absorb reflections without attenuating signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single on-die termination structure is used per high-speed signaling line, then the device complexity is reduced and manufacturing is simplified, but signaling margins are reduced and bit error rates increase due to impedance discontinuity and signal attenuation
Solution Approach 1:
The patent divides the termination structure into multiple segmented termination circuits (first termination circuit and second termination circuit) with different termination impedance values. Each segment can be independently controlled by separate control signals, allowing the system to select appropriate termination levels for different operating conditions. This segmentation resolves the contradiction by providing multiple termination options without requiring a completely complex redesign, thereby improving signaling margin while maintaining reasonable device complexity.
Solution Approach 2:
The patent implements dynamic termination control by introducing control circuits that can switch between different termination impedance values based on operational requirements. The first and second control signals dynamically enable or disable different termination circuits, allowing the termination impedance to adapt to varying signal conditions. This dynamic adjustment improves signaling margin and reduces bit error rates while keeping the overall structure manageable through systematic control.
2Reliability
If multiple graduated on-die termination structures are implemented per high-speed signaling line, then signaling margins are enhanced and bit error rates are reduced, but device complexity increases
Solution Approach 1:
The patent applies local quality by providing different termination impedance values at different locations or configurations within the same device. The first termination circuit provides a first termination impedance value while the second termination circuit provides a second termination impedance value. This local differentiation allows optimal termination for specific signal conditions without requiring complete system redesign, thereby enhancing signaling margin while controlling the growth of device complexity through targeted local improvements.
Solution Approach 2:
The patent changes the termination impedance parameter by providing multiple termination circuits with different impedance values. By switching between the first termination impedance value and the second termination impedance value based on control signals, the system optimizes signaling performance for different operational scenarios. This parameter variation enhances signaling margin and reduces bit error rates while maintaining manageable device complexity through systematic parameter control.
3Loss of energy
If on-die terminations are decoupled from the data path to avoid signal attenuation, then signal strength is preserved, but impedance discontinuity occurs at the selected memory module
Solution Approach 1:
The patent resolves the contradiction between signal attenuation and impedance continuity through dynamic termination control. Control circuits monitor operational conditions and dynamically switch between different termination circuits based on whether the memory module is selected or unselected. During write operations, the appropriate termination circuit is activated to maintain impedance continuity, while during read operations or when unselected, terminations are decoupled to preserve signal strength. This dynamic adjustment eliminates both signal attenuation and impedance discontinuity issues.
Solution Approach 2:
The patent implements feedback control by using control circuits that respond to operational states (selected/unselected memory modules, write/read operations) to adjust termination configurations. The control signals are generated based on feedback from the operational context, ensuring that termination impedance is optimized for current conditions. This feedback mechanism maintains impedance continuity when needed and prevents signal attenuation when appropriate, resolving the contradiction between these two requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances signaling margins, reduces bit error rates, and provides additional headroom for increased signaling rates by dynamically adjusting terminations between memory modules.
Implementation Method 1
terminating elements have been implemented by discrete resistors connected to metal traces on a mother board or other printed circuit board
Data Source
AI summary
A memory controller for controlling integrated circuit memory devices that have on-die termination. The memory controller includes an output driver to output a first data signal onto a data line, and termination control circuitry to output termination control signals to integrated circuit memory devices coupled to the data line. The termination control signals control coupling and decoupling of termination elements to the data line according to which of the plurality of integrated circuit memory devices is selected to receive the first data signal. In particular, the termination control signals specify coupling a termination element having an impedance indicated by a first termination value to the data line within one of the plurality of integrated circuit memory devices selected to receive the first data signal, and wherein the termination control signals further specify coupling a termination element having an impedance indicated by a second termination value to the data line within at least one other of the plurality of integrated circuit memory devices.